高性能螺线管微电感的制作

利用MEMS技术制作了高性能的空芯螺线管型射频微机械电感.这种微电感采用铜线圈以减小线圈寄生电阻,整个微电感的面积是880μm×350μm,与平面螺旋型微电感相比,有效地节省了芯片面积.测试结果表明,微电感在较宽的工作频率范围内具有高Q值,微电感最大Q值为38(@6GHz),对应的电感量为1.82nH.     

高性能螺线管微电感的制作

利用MEMS技术制作了高性能的空芯螺线管型射频微机械电感.这种微电感采用铜线圈以减小线圈寄生电阻,整个微电感的面积是880μm×350μm,与平面螺旋型微电感相比,有效地节省了芯片面积.测试结果表明,微电感在较宽的工作频率范围内具有高Q值,微电感最大Q值为38(@6GHz),对应的电感量为1.82nH.     

集成双层平面电感的单片DC/DC转换器设计

采用0.35μm标准CMOS工艺设计了3.3V/1.5V单片低压Buck转换器,开关频率为150MHz.本文采用了电压型脉宽调制的反馈控制模式,克服了频率提高所带来的转换器系统不稳定问题.对双层平面螺旋电感进行了设计与优化,获得品质因数2.6,电感值28nH的双层平面电感.模拟结果表明,对应于不同输入电压或不同负载,转换器系统工作稳定,输入调整率-40dB,输出调整率-60dB.输出电压纹波平均值可以控制在额定值75mV,转换效率71%.     

改善硅基螺旋电感品质因数的厚铝膜干法刻蚀

提出了一种用于改善硅基螺旋电感品质因数的厚铝膜干法刻蚀技术;这种技术利用氧化硅和光刻胶双层复合掩模来掩蔽厚铝的干法刻蚀,完全兼容于CMOS工艺;应用于双层铝布线,实现了最大厚度达到6μm的顶层铝,显著地减小了螺旋电感的串联电阻,提高了品质因数;该技术同高阻SOI衬底技术相结合,制造的10nH螺旋电感的最大品质因数达到8.6。     

隔层不交叠多层电感分析与设计

提出了一种隔层不重叠的新型结构片上螺旋电感,其实现工艺与标准CMOS多层布线技术兼容.结合螺旋电感的集总模型,利用电磁场仿真软件HFSS进行了该器件的模拟仿真,与相同结构参数和工艺参数的传统不隔层交叠多层电感相比,提出的新型电感在品质因子、自谐振频率、3dB带宽等性能参数上明显改善,其中电感品质因子提高3.5％,带宽增...     

标准数字CMOS工艺中LC谐振回路的改进和应用

提出了一种在标准数字CMOS工艺条件下,提高片上螺旋电感性能的实用方法,以及在缺少双层多晶硅电容的情况下,可以大大节约芯片面积的一种电容实现方法.介绍了这两种方法在电路设计中的一种应用,即利用0.35μm 1P4M标准数字CMOS工艺实现的、单片集成的LC压控振荡器.     

标准数字CMOS工艺中LC谐振回路的改进和应用

提出了一种在标准数字CMOS工艺条件下,提高片上螺旋电感性能的实用方法,以及在缺少双层多晶硅电容的情况下,可以大大节约芯片面积的一种电容实现方法.介绍了这两种方法在电路设计中的一种应用,即利用0 .35 μm1P4 M标准数字CMOS工艺实现的、单片集成的L C压控振荡器.     

新颖的常规硅工艺实现的侧向螺线型片上集成电感

提出了一种用常规硅工艺实现的片上集成电感的螺线型新结构．制造工艺使用标准双层金属布线的常规硅工艺．测量了螺线型集成电感的S参数，从测量数据计算了集成电感的参量．实验的侧向螺线型片上集成电感的Q值峰值为1.3，电感量为22nH．对用两层金属层实现的侧向螺线型片上集成电感和单层金属的常规平面螺旋电感的实验结果进行了比较，电感量和Q值与常规平面螺旋电感有可比性．     

新颖的常规硅工艺实现的侧向螺线型片上集成电感

提出了一种用常规硅工艺实现的片上集成电感的螺线型新结构．制造工艺使用标准双层金属布线的常规硅工艺．测量了螺线型集成电感的S参数，从测量数据计算了集成电感的参量．实验的侧向螺线型片上集成电感的Q值峰值为1.3，电感量为22nH．对用两层金属层实现的侧向螺线型片上集成电感和单层金属的常规平面螺旋电感的实验结果进行了比较，电感量和Q值与常规平面螺旋电感有可比性．     

新颖的常规硅工艺实现的侧向螺线型征上集成电感

提出了一种用常规硅工艺实现的片上集成电感的螺线型新结构。制造工艺使用标准双层金属布线的常规硅工艺。测量了螺线型集成电感的S参数，从测量数据计算了集成电感的参量。实验的侧向螺线型片上集成电感的Q值峰值为1.3，电感量为2.2nH。对用两层金属层实现的侧向螺线片上集成电感和单层金属的常规平面螺旋电感的实验结果进行了比较，电感量和Q值与常规平面螺旋电感有可比性。     

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f_SR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q_max. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced     

Flip chip assembled MEMS inductors

High performance suspended MEMS inductors produced using a flip chip assembly approach are described. An inductor structure is fabricated on a carrier and then flip chip assembled onto a substrate to form a suspended inductor for RF-IC applications with significant improvement in Q-factor and frequency of operation over the conventional IC inductors. A spiral MEMS inductor has been successfully produced on a silicon substrate with an air gap of 26 /spl mu/m between the inductor structure and the substrate. The inductance of the device was measured to be /spl sim/2 nH and a maximum Q-factor of 19 at /spl sim/2.5 GHz was obtained after pad/connector de-embedding.     

Design, Optimization of RF Spiral Inductors Using Scalable Compact and Accurate Models

This paper presents a practical and structured approach to the design and optimization of RF spiral inductors. The accuracy of proposed modified accurate distributed and scalable compact lumped models are quantitatively compared with experimental results. Based on the new scalable compact lumped model, a quality factor optimization engine is verified. The inductors under study include single/double layer inductors, metallization shunted as well as octagonal shaped inductors. Experimental results suggest that the new modified accurate distributed model is more accurate than existing models for predicting spiral inductor performance to even beyond resonance frequencies. In addition, using a self developed optimization engine, the new scalable compact model is sufficiently accurate in determining the optimum inductor geometry. Consequently, a web-based program (SISOP) is developed to provide RF designers total solution to spiral inductor design, optimization and integration of spiral inductor model into their lump circuit simulators.     

隐埋电感工艺的开发与研究

通过蚀刻铜箔结合导通孔连接的方法在四层PCB中制得了大小从120 nH到1 400 nH的三维螺旋隐埋电感,品质因数分别为6～31(测量频率为1 MHz)。所制得隐埋电感既包括垂直轴线,也包括水平轴线三维螺旋隐埋电感线圈;既包括平面螺旋电感和三维螺旋线圈,又包括两者的复合。另外通过对比研究不同物理参数对垂直轴线三维隐埋电感的影响,结果发现在相同周长的情况下,圆形电感略优于方形电感;电感大小和线圈的面积及圈数成正比,与线圈间距成反比;品质因数随着线圈的面积、圈数和线圈间距的变化而略有变化。     

S-parameter formulation of quality factor for a spiral inductor in generalized two-port configuration

This paper formulates various quality (Q) factors associated with the applications of on-chip spiral inductors to radio-frequency integrated circuits using S-parameters. The formulations start with the Q factor of a spiral inductor in a generalized two-port configuration based on a new complex-power approach and then extend to the Q factors of a tank and matching circuits that use the spiral inductors. In the demonstration, the two-port S-parameters for a series of CMOS spiral inductors have been measured to further generate such various Q factors for a many-sided evaluation of the inductor performance.     

Variable inductance multilayer inductor with MOSFET switch control

A variable monolithic inductor having a stacked spiral inductor connected with MOSFET switches is proposed and fabricated in a 0.18 /spl mu/m, one-poly-six-metal (1P6M) standard CMOS process. By controlling a voltage of the MOSFET switch, the proposed three-stacked inductor demonstrates a continuously variable inductance of from 8 to 23 nH at 2.4 GHz, and due to its stacked structure, it takes less than 50% of the chip area compared with conventional single layer inductors. With its compact size and variable inductance feature, the proposed variable inductor is a prospective key component for the multiband RF circuits such as electrically controllable matching circuits and wide tuning range voltage controlled oscillators (VCOs).     

High Q multilayer spiral inductor on silicon chip for 5/spl sim/6 GHz

High Q-values of spiral inductors at frequency around 5/spl sim/6 GHz have been achieved with a multilayer spiral (MLS) structure on a high loss silicon substrate. Compared to a one-layer spiral (OLS) inductor, the Q-value of a 4-nH inductor has been improved by about 80% at 5.65 GHz. The impact of the structure on Q-value and resonant frequency has been analyzed, which shows that an optimal height for the via of MLS inductors should be considered when inductors are designed. The fabrication process is compatible with Cu/SiO/sub 2/ interconnect technology.     

Metallization proximity studies for copper spiral inductors on silicon

The impacts of metallization proximity for copper spiral inductors on silicon have been investigated in this paper. Performance of the spiral inductor versus area consumption tradeoff with respect to its core diameter is evaluated quantitatively for the first time. Effects of the inductor's proximate grounded metallization on its overall inductive performance are also analyzed.