基于2DMesh拓扑结构的NoC模拟器设计

片上网络模拟器的设计涉及到片上网络的拓扑结构、路由器结构、路由算法、性能分析等诸多方面。从NoC模拟器设计的角度,研究并讨论模拟器所采用的拓扑结构,路由器结构及数据包格式。介绍拓扑结构模拟、IP核模拟、路由模拟,并且用面向对象语言C＋＋实现一个NoC模拟器系统。     

一种二维片上网络路由器的设计实现

片上网络(Network on Chip, NoC)作为解决众核芯片互连的主流方案,其性能很大程度上取决于网络的拓扑结构。而网络拓扑结构的效能受到网络路由器的直接影响。因此,基于特定拓扑结构的路由器设计实现具有非常重要的研究意义。因此将XY路由算法应用于路由器节点中,设计了基于2D Mesh拓扑结构、轮询仲裁机制与虫孔交换流控的片上网络路由器,并使用Modelsim对路由器进行了功能验证。实验结果表明,设计的路由器能满足微片数据的处理,能够正确的收发数据包。     

一种改进的BFT型片上网络拓扑结构

针对片上网络(NoC)资源节点之间通信的局部性,提出改进的蝴蝶型胖树(BFT)拓扑结构XBFT及相应的路由算法.该结构在BFT结构的基础上改变边的连接关系,减少了路由节点数和物理连接链路数,理论分析表明,在64个IP核的NoC中,XBFT较BFT路由器数目减少了14.3％,物理链路数减少了10.7％,XBFT结构比BF...     

支持双拓扑结构的片上网络评估高层仿真平台

为实现高效的NoC（片上网络）性能评估, 缩短系统芯片的开发周期, 针对时钟精确级的NoC仿真方法进行研究, 提出了一种新型的高层次、高效率仿真平台, 与仅支持网格拓扑结构的传统仿真器相比, 其创新地支持了网格和环型双拓扑结构的性能评估, 同时支持虚通道扩展的路由器结构设计, 能快速得到网络的延迟、吞吐率、功耗等性能结果。实验结果表明, 该仿真平台能准确模拟NoC功能行为, 快速获得其仿真性能, 为NoC设计验证提供了高效的方法。     

Storus:一个二维片上网络拓扑结构

随着CMOS工艺集成度持续不断提高,单片多处理器正在成为高性能处理器结构的发展趋势,现有的片上总线结构已不足以满足片上系统设计的互连需求,近年来提出了片上网络这一新的互连结构,片上网络需要解决的问题有:选择合适的拓扑结构、路由算法、流控机制等等.文中为片上网络结构提供了一个新的拓扑结构Storus以及路由算法L2,并使用多种负载模式、多种流控机制对Storus与Torus结构进行模拟分析.模拟结果显示,Storus的平均路由延时约比Torus小2%～15%,使用热点负载模拟时,Storus的饱和吞吐量约为Torus结构的1.2～1.5倍.     

片上网络拓扑结构

介绍了片上网络（NoC）拓扑结构的相关研究进展。对NoC拓扑结构进行了分类，详细分析了各种网络拓扑的相关特性。从拓扑结构的角度出发，介绍了几种典型的NoC实例，归纳了相关的设计方法。最后，探讨了NoC拓扑结构的发展方向。     

NoC节点编码及路由算法的研究

NoC的设计和实现受到芯片的面积、功耗、深亚微米效应的限制.将拓扑结构和节点编码相结合,提出一种基于约翰逊码的二维平面编码.该编码隐含了Torus网络拓扑结构以及网络节点之间的连接关系并且有很好的扩展性,能够简化Torus拓扑结构上路由算法的实现和降低硬件成本.基于此编码和利用X-Y路由的路由确定性特点,提出改进X-Y路由,在中间节点只需要3或5个逻辑运算,降低路由的计算复杂性和硬件成本.最后,进行了节点结构设计.提出的编码不仅用于NoC的路由方面而且在NoC任务映射方面有重要应用.     

3D NoC网络架构设计

在三维片上网络(3D NoC)设计中,层与层之间通信机制的优劣将影响整个3D NoC系统的性能。为此,在GEMS仿真平台基础上,提出一种低硬件资源消耗、高性能的总线架构,改进路由设计,构造基于总线的3D NoC的路由器。实验结果表明,该架构可提高常见算法的加速比,改善系统的整体性能。     

大规模并行网络模拟系统

为了提高并行网络模拟的真实性、可用性以及运行效率,该文设计并实现了并行分布式互联网模拟使用系统,它可以用网络测量工具获得真实网络数据作为模拟基础,采用优化的拓扑网络划分方法对模拟任务进行划分,采用基于边界路由器的子网间路由配置实现准确的路由模拟,运行脚本的自动生成以及模拟拓扑图的可视化。通过该并行网络模拟使用系统可以实现大规模网络安全事件的模拟,如蠕虫扩散、DDoS攻击等。     

基于路由器解析式模型的NoC网络性能分析方法

建立一种高效的片上网络(NoC)性能分析方法对NoC早期的系统设计分析具有重要的指导意义.首先从NoC路由器工作原理出发,对报文传输中的各种阻塞现象进行分析,建立了基于M/G/1/N排队系统的路由器模型;然后提出NoC网络性能分析算法,并且给出了传输延迟、饱和吞吐率等参数的解析表达式.与时钟精度仿真结果比较表明,该方法分析误差约为6.9%,但分析效率提高了约200倍.该方法适用于指导程序NoC拓扑映射,在获取最优映射方案同时,可有效地挖掘网络通信瓶颈.     

片上网络路由节点优化设计

针对虚输出队列结构的路由节点所构成的片上网络(NoC),提出了一种定制化路由节点中各个虚拟通道缓存大小的方法,以提高片上网络的整体通信性能。在有限的片上缓存资源约束下,分析各个虚输入队列中缓存大小对数据通过片上网络的平均延迟的影响,并在此基础上提出一种缓存资源配置方法,以便将缓存资源分配到片上网络通信瓶颈处,从而在不增加缓存资源开销的情况下提高片上网络的通信性能。最后通过仿真验证了路由节点优化设计对提高片上网络性能的可行性,并同未优化的路由节点构成的片上网络性能进行了比较。     

An Efficient Network-on-Chip Router for Dataflow Architecture

Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip (NoC). Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture: multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.     

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Network-on-Chip (NoC) is widely used as a communication scheme in modern many-core systems. To guarantee the reliability of communication, effective fault tolerant techniques are critical for an NoC. In this paper, a novel fault tolerant architecture employing redundant routers is proposed to maintain the functionality of a network in the presence of failures. This architecture consists of a mesh of 2 × 2 router blocks with a spare router placed in the center of each block. This spare router provides a viable alternative when a router fails in a block. The proposed fault-tolerant architecture is therefore referred to as a quad-spare mesh. The quad-spare mesh can be dynamically reconfigured by changing control signals without altering the underlying topology. This dynamic reconfiguration and its corresponding routing algorithm are demonstrated in detail. Since the topology after reconfiguration is consistent with the original error-free 2D mesh, the proposed design is transparent to operating systems and application software. Experimental results show that the proposed design achieves significant improvements on reliability compared with those reported in the literature. Comparing the error-free system with a single router failure case, the throughput only decreases by 5.19% and latency increases by 2.40%, with about 45.9% hardware redundancy.     

A High-Throughput Distributed Shared-Buffer NoC Router

Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or an output-buffered router (OBR). OBRs are attractive because they have higher throughput and lower queuing delays under high loads than IBRs. However, a direct implementation of OBRs requires a router speedup equal to the number of ports, making such a design prohibitive given the aggressive clocking and power budgets of most NoC applications. In this letter, we propose a new router design that aims to emulate an OBR practically based on a distributed shared-buffer (DSB) router architecture. We introduce innovations to address the unique constraints of NoCs, including efficient pipelining and novel flow control. Our DSB design can achieve significantly higher bandwidth at saturation, with an improvement of up to 20% when compared to a state-of-the-art pipelined IBR with the same amount of buffering, and our proposed microarchitecture can achieve up to 94% of the ideal saturation throughput.     

用NS2评估片上网络体系结构的性能

随着SoC复杂度的不断提高,总线互连结构面临着越来越严峻的挑战,因此,以网络互连为特点的NoC应运而生。分析了影响NoC性能的几项重要指标,并用网络仿真软件NS2对几种常用拓扑结构的几项性能参数进行了评估,得出了在进行NoC设计时的指导性结论：结合具体的设计,对传输延迟、吞吐量、面积、功耗和可重用性等性能参数进行折衷考虑后选取合适的体系结构。     

An analytical model for Network-on-Chip with finite input buffer

An analytical model is proposed for input buffer router architecture Network-on-Chip (NoC) with finite size buffers. The model is developed based on M/G/1/K queuing theory and takes into consideration the restriction of buffer sizes in NoC. It analyzes the packet’s sojourn time in each buffer and calculates the packets average latency in NoC The validity of the model is verified through simulation. By comparing our analytical outcomes to the simulation results, we show that the proposed model successfully captures the performance characteristics of NoC, which provides an efficient performance analysis tool for NoC design.     

A hardwired NoC infrastructure for embedded systems on FPGAs

A hardwired network-on-chip based on a modified Fat Tree (MFT) topology is proposed as a communication infrastructure for future FPGAs. With extremely simple routing, such an infra structure would greatly enhance the ongoing trend of embedded systems implementation using multi-cores on FPGAs. An efficient H-tree based floor plan that naturally follows the MFT construction methodology was developed. Several instances of the proposed NoC were implemented with various inter-routers links progression schemes combined with very simple router architecture and efficient client network interface (CNI). The performance of all these implementations was evaluated using a cycle-accurate simulator for various combinations of NoC sizes and traffic models. Also a new data transfer circuit for transferring data between clients and NoC operating at different (unrelated) clock frequencies has been developed. Allowing data transfer at one data per cycle, the operation of this circuit has been verified using gate-level simulations for several ratios of NoC/client clock frequencies.     

Buffer planning for application-specific networks-on-chip design

Networks-on-chip (NoC) is a promising communication architecture for next generation SoC. The size of buffer used in on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each router buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements. Supported by the National Natural Science Foundation of China (Grant No. 60803018)     

Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs

Rapid growth in the number of Intellectual Property (IP) cores in System-on-Chip (SoC) resulted in the need for effective and scalable interconnect scheme for system components – Network-on-Chip (NoC). Router is a key component in an NoC design that impacts the overall area utilization. It is crucial to evaluate the area efficiency of NoC routers. In this paper, we evaluate and compare two recent NoC routers for Field Programmable Gated Arrays (FPGAs). The first one is generated using the automated NoC synthesis tool CONfigurable NEtwork Creation Tool (CONNECT). The second one is an NoC router manually designed using VHDL and synthesized Altera Quartus II CAD tool. Three NoC topologies namely ring, mesh and torus are used for evaluating the two routers based on area utilization metric. The routers are evaluated by varying the node sizes from 4 to 16 for each topology. For smaller NoC topologies, CONNECT router uses less area but as the NoC size increases manual router design provides up to 85% reduction in area utilization. The results presented in this paper will be useful to designers interested in NoC implementation on FPGAs.