一种低相噪CMOS环形振荡器设计

设计了一种带有正交输出,频率为900MHz的两级低相噪环形振荡器,电路设计采用0.18μm CMOS工艺,电源电压为1.8V.环形振荡器的调谐范围随控制电压从0V的1460MHz到电源电压1.8V的720MHz发生变化,并且具有较好的线性度.在频率为900MHz、偏移载波频率为600kHz的情况下,环形振荡器的相位噪声为-108dBc/Hz,功耗为18mW.在与其它环形振荡器的比较中,yynw环形振荡器显示了较好的性能参数.     

采用抗混叠滤波器的高性能、12bit、500MS/s宽带接收机(CN0238)

电路功能与优势 电路是基于超低噪声差分放大器驱动器ADA4960-1和12 bit、500 MS/s模数转换器AD9434的宽带接收机前端.因是原理示意图,未显示所有连接和去耦. 三阶巴特沃兹抗混叠滤波器基于放大器和ADC的性能以及接口要求而优化.由滤波器网络、变压器和其他阻性元件引起的总插入损耗仅为1.2 dB.整体电路带宽为290 MHz,通带平坦度为1 dB.在140 MHz模拟输入下测得的SNR和SFDR分别为64.1 dBFS和70.4 dBc.     

一种基于MDAC优化的低功耗流水线A/D转换器

设计了一种低功耗16位100 MS/s的流水线A/D转换器。通过采用级间电容缩减技术,并优化增益数模转换器(MDAC)的结构,降低采样电容的面积。流水线前两级采用高性能低功耗运算跨导放大器(OTA),通过动态偏置技术进一步降低功耗。芯片采用0.18μm混合信号CMOS工艺,1.8 V单电源供电。经测试,流水线A/D转换器在5 MHz的输入频率下,信噪失真比(SNDR)为74.2 dB,无杂散动态范围(SFDR)为91.9 dB,整体功耗为210 mW。     

一种单电源供电的十位双积分A/D转换器

设计了一种改进的双积分A/D转换器,通过采取2种模式积分的方法实现了+5V单电源供电,克服了传统双积分A/D转换器需要双电源的弊端。重点考虑可处理输入信号范围以及功耗的优化,并使用栅压自举开关保证了A/D转换的精度。整体电路设计基于CSMC0.5μm 2P3M CMOS工艺,使用Cadence Spectre进行仿真,在5V供电情况下达到10bit精度,转换速率>10Kb/s,输入电压范围达到0~5V,INL<1/2LSB,系统功耗2.636mW。     

A/D转换器MAX176与单片机的接口技术

MAX176是美国美信公司制造的12位串行A/D转换器,片内含有采样保持器,能将-5～ 5V之间的模拟信号快速捕获并转换为数字信号(捕获时间为0.4μs,最长转换时间为3.5μs)。 MAX176的引脚如图1所示。VDD为 5 V电源端,AIN为模拟信号(-5～ 5 V)输入端,VREF为-5 V参考电压输出端,GND为接地端,DATA为数据输出端,CLOCK(用于输出转换结果)为时钟脉冲(100kHz～4 MHz)输入端,CONVT为转换控制输入端,VSS为-12 V或-15 V电源端。     

一种廉价高精密基准电压源

<正> 适用于单片机A/D、D/A 转换器参考电源及传感器桥压的高精密基准电压源电路原理图如图l所示。电路工作原理是:基准电压源U_1的输出为A_1提供+2.5V 基准电压并接至其同相输入端,经A_1放大,在V_(01)点输出+5V、20mA 供A/D、D/A 转换器用。A_2,     

高精度低温度系数带隙基准电压源的设计

基于0.5μm双层多晶双层铝CMOS工艺,采用共源共栅电流镜结构和基极电流补偿方法,设计了一种新颖的高性能带隙电压基准.结果表明,在温度-25℃～125℃范围,基准电压温度系数为15.3×10-6V/℃,低频时,电源抑制比可达-80db.该电路可做为A/D和D/A转换器中的基准电压源.     

基于STC单片机的数控通信直流电源设计

采用STC12C5A60S2单片机,设计了用于通信机房的12-48V可调高精度数控直流电源。主要包括键盘输入,LED显示,PWM波输出,功率输出,A/D转换等模块。该电源采用了10位高精度A/D对输出电压进行采用,实现了闭环控制,具有电压调节方便,精度高等优点,能够满足通信机房对电源电压及精度的要求。     

12管低相噪CMOS环形振荡器

提出了一种12管宽线性调谐范围低噪声低功耗的环形振荡器结构。电路设计采用0.18μm的标准CMOS工艺,电源电压为1.8V。SpectreRF仿真结果显示该环形振荡器在27.17MHz到2.062GHz的宽调谐范围内具有良好的线性度。在频率为900MHz、偏移频率为600kHz时,该环形振荡器的相位噪声为-111.1dBc/Hz,功耗为38mW。通过SpectreRF仿真与目前流行的环形振荡器进行比较,本文提出的环形振荡器结构简单、性能优越。     

一种用于流水线ADC的高速采样保持电路

介绍了一种适用于10位80MS/s流水线模数转换器(Pipelined ADC)的采样/保持(S/H)电路。该电路为开关电容结构,以0.25μm CMOS工艺实现。采用栅源电压恒定的栅压自举开关和底极板采样技术,极大地减小了采样的非线性失真。基于该S/H电路的流水线A/D转换器在80MHz采样率下,输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为84.9dB,有效位数(ENOB)达到10位。     

一种13bit 40MS/s采样保持电路设计

设计了一个用于13bit40MS/s流水线ADC中的采样保持电路。该电路采用电容翻转结构,主运算放大器采用增益提高型折叠式共源共栅结构,以满足高速和高精度的要求。为减小与输入信号相关的非线性失真以获得良好的线性度,采用栅压自举开关。采用电源电压为3.3V的TSMC0.18μm工艺对电路进行设计和仿真,仿真结果表明,在40MHz的采样频率下,采用保持电路的SNDR达到84.8dB,SFDR达到92dB。     

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, ?Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post‐layout simulation results, phase noise is ?110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and ?113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation‐mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure

A multiphase LC voltage-controlled oscillator(VCO) with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery(CDR) circuit for 40 Gb/s optical communications system.Compared with the traditional eight-phase oscillator,this capacitive coupling structure can decrease the number of inductors to half and only of four inductors.The VCO is designed and taped out in TSMC 65 nm CMOS technology.Measurement results show the phase noise is 105.95 dBc/Hz at 1MHz offset from a carrier frequency of 10 GHz.The chip area of VCO is 480 μm×700 μm and the VCO core power dissipation is 4.8 mW with the 1.0 V supply voltage.     

一种射频接收芯片中的低相位噪声压控振荡器

本文介绍了一种适用于ASK幅移键控接收器芯片中锁相环电路,集成于芯片内的LC压控振荡器,它的LC振荡电路采用了一种增强型的特别结构。芯片采用锁相环电路来产生本振信号。接收器通过它工作在290MHz到470MHz的ISM频段。锁相环中的VCO采用了差分对结构的LC压控振荡器结构,在1V到5V的控制电压下能产生290到470的可调频率,输出功率为2.20到2.30dBm。该VCO采用了增强型结构的LC振荡电路以得到更高的Q值来减小相位噪声,采用这种特殊结构,它能在433MHz载波的100kHz偏移范围内实现-99.7dBc/Hz的相位噪声。与普通LC振荡电路结构相比,该结构能使VCO相位噪声减小3dBc以上。且由于该电路由较少的有源器件组成,因此该VCO有着非常低的功耗和成本。     

A current‐mode tunable low‐supply‐voltage ring oscillator

A new circuit topology using a current‐mode low‐pass filter for sinusoids has been presented. The technique is relatively simple, in the proposed circuit, only three identical current‐mode low‐pass filters are connected to each other to realize the small signal path. No external passive components are required except for three capacitors. When compared with LC oscillators, the die area of this work, without inductors, is much smaller. When compared with voltage‐mode ring oscillators, the supply voltage of this work is much lower. As a particular example, a 2.4 GHz, 1.2‐V power supply, 5‐mW sinusoidal oscillator is demonstrated. The oscillation frequency is tuned by the value of that three capacitors, over ～900 MHz, and the tuning range is 37.5%. The phase noise results in ?94 and ?120 dBc/Hz at 1 and 10 MHz from the carrier, respectively. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.     

A design approach of higher oscillation VCO made of CS amplifier with varying active load

This article proposes a design approach of common source (CS) amplifier based Voltage Controlled Oscillator (VCO) to derive higher oscillation frequency. The working feature is such that, the active load of CS amplifier is varied to modulate the flow of current based on a bias circuit steered by an external controlled voltage (V_ctrl), which controls the delay of each stage and thereby regulates the oscillation frequency. The circuit is designed and analyzed on Cadence Virtuoso platform at a supply voltage of 1.2 V for 90 nm CMOS to read a device footprint of 0.105 mm², which offers a power burn and frequency of 2.092 mW and 9.21 GHz respectively with a phase noise and output noise of − 137.9 dBc/Hz and − 168.40 dB at 1 MHz offset frequency. To justify the reliability of the circuit we have conducted worst case analysis by considering effect of power delivery network (PDN) and corner variation along with 500 runs of Monte Carlo. The design is also introduced under 28 nm UMC to validate its scalability with technology trends.

     

Realization of a VCO for WLAN applications using 0.35 μm‐siGe BICMOS technology

In this article, a 4.5–5.8 GHz, ?G_m LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with Austria MicroSystems 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe heterojunction bipolar transistors (HBTs). According to measurement results, phase noise is ?102.3 dBc/Hz at 1 MHz offset from 5 GHz carrier frequency. A linear, 1300 MHz tuning range is obtained utilizing accumulation‐mode varactors. Phase noise is relatively low because of the advantage of differential tuning concept. Output power of the fundamental frequency changes between ?1.6 and 0.9 dBm depending on the tuning voltage. Average second and third harmonic levels are ?25 and ?41 dBm, respectively. The circuit draws 14 mA DC current from 3.3 V supply including buffer circuits leading to a total power dissipation of 46.2 mW. The prototype VCO occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.     

Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N‐metal oxide semiconductor (NMOS) and P‐metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct‐current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is ?114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm² including the bond pads.     

适用于频率综合器的宽带低相噪VCO设计

针对频率综合器在宽调谐范围下相位噪声变差的问题,设计了一款适用于频率综合器的宽调谐范围低相位噪声的压控振荡器;采用180nm BiCMOS工艺,运用可变电容阵列和开关电容阵列实现宽调谐范围;通过加入降噪模块,滤除压控振荡器产生的二次谐波和三次谐波,增大输出振幅,降低相位噪声;并在压控振荡器输出端加入输出缓冲器,降低频率综合器其他器件对压控振荡器的影响;通过Cadence软件对压控振荡器进行仿真,仿真结果表明：调谐电压为0.3~3V,压控振荡器的输出频率范围为2.3~3.5GHz;当压控振荡器的中心频率为3.31GHz时,在偏离中心频率10kHz、100kHz和1MHz处的相位噪声分别为-93.21dBc/Hz,-117.03dBc/Hz,-137.41dBc/Hz,功耗7.66mW;在较宽的频率范围内,取得良好的相位噪声抑制,提高压控振荡器的噪声性能,满足宽带低相噪频率综合器的应用需求。     

一种用于人体传感器网络的接收器模拟前端

设计了一种用于人体传感器网络的低功耗接收器模拟前端,电路物理层信道利用人体进行通信,并采用了一种宽带信号传输技术,可以在0.8 V电压供电,100 mV输入敏感度条件下传输20 Mb/s的数据。片上的电压偏置电路提供了50Ω的输入阻抗。放大器采用了一种低压低功耗的Cascode结构,具有58 dB的增益,25 MHz的增益带宽积。另外采用了一种结构简单,功耗极低的电流反馈型Schmitt触发器。电路采用SMIC0.13μm标准CMOS工艺设计,面积0.02 mm2,供电电压0.8 V,功耗仅为2.2 mW。