微热板阵列的热干扰

针对微热板阵列建立了热路模型,并对热干扰进行分析.结果表明,由于微热板悬窄结构的热阻比硅芯片的热阻高3个数量级.因此微热板阵列芯片的热干扰温度取决于封装对环境的热阻,而芯片上器件的间距对热干扰温度的影响可以忽略.研制了3种布局、T05和DIPl6两种封装形式的微热板阵列,并对阵列中的热干扰问题进行了实验测试.测试数据验证了热路模型的结论.因此,减小微热板阵列或集成芯片的热干扰的关键在于,尽可能增大微热板悬空结构的热阻以及选用热阻小的封装形式.     

多芯片组件（MCM）的热模拟研究

介绍了MCM的封装热阻及相应的几种热阻计算方法。利用有限元分析软件ANSYS对多芯片组件(MCM)进行了热模拟。在常用两种MCM结构的热流模型基础上，分析并比较了这两种热模型差异及对散热的影响。根据ANSYS模拟结果，讨论了空气流速、基板热导率及其厚度、芯片粘结层热导率及其厚度对MCM封装热特性的影响，分析了控制MCM封装内、外散热的主要因素。     

倒装芯片集成电力电子模块的热设计

将倒装芯片(Flip Chip, FC)技术引入三维集成电力电子模块(Integrated Power Electronic Module,IPEM)的封装,可构建FC-IPEM.在实验室完成了由两只球栅阵列芯片尺寸封装MOSFET和驱动、保护等电路构成的半桥FC-IPEM.针对半桥FC-IPEM,建立半桥FC-IPEM的一维热阻模型,分析模块主要的热阻来源.运用FLOTHERM软件进行三维仿真,得到模块温度分布结果,给出优化模块热性能的依据.     

基于热测试芯片的2.5D封装热阻测试技术研究

2.5D多芯片高密度封装中,多热源复杂热流边界、相邻热源热耦合增强,高精准的热阻测试与仿真模拟验证是封装热设计的关键。设计开发了基于百微米级发热模拟单元的热测试验证芯片（TTC）,并基于多热点功率驱动电路系统和多通道高速采集温度标测系统,实现了2.5D多芯片实际热生成的等效模拟与芯片温度的多点原位监测。通过将实际热测试结构函数导入热仿真软件,实现了仿真模型参数的拟合校准,采用热阻矩阵法表征多芯片封装热耦合叠加效应,实现了多热源封装热阻等效表征。结果表明,多芯片封装自热阻和耦合热阻均随着芯片功率密度的增加而提高,芯片的热点分布对封装热阻值的影响更为显著,因此模拟实际芯片发热状态、建立等效热仿真模型是实现高精准封装热仿真和散热结构设计的关键。     

基于结构函数的大功率整流管封装内部热阻分析

在对大功率整流管(以下简称器件)进行瞬态热阻抗测试的基础上,基于结构函数分析技术建立器件由热阻、热容组成的RC热模型,并结合器件的封装结构对其内部热阻进行分析,得到了器件各层材料的内部热阻分别为:芯片0.12℃/W、焊接层0.18℃/W、绝缘层0.21℃/W、管座0.67℃/W。研究表明,利用结构函数分析大功率整流管内部热阻是一种可靠、有效的方法,对于器件封装结构的热设计具有重要意义。     

微系统热阻模型研究及其应用

系统级封装(SIP)实现了高密度、高集成度封装技术,同时散热问题备受关注,热设计中芯片结温预测十分重要.本文采用有限元仿真方法,建立了一种自然对流环境下微系统热阻模型,并通过模型中热阻矩阵预测多芯片总功耗相同条件下的各芯片结温,同时利用热阻测试试验和有限元仿真方法对预测结温进行验证,结果表明热阻矩阵模型预测芯片结温与热阻测试试验和有限元仿真结果误差分别小于2%和5%.但同时发现该热阻矩阵模型的不通用性,对于总功耗变化的多芯片结温,预测结果偏差较大.通过不同总功耗下各热阻矩阵的函数关系建立拟合曲线并修正热阻矩阵模型,修正后的结环境热阻矩阵适用于不同总功率条件、各芯片不同功率条件下的芯片结温预测,预测结果与热阻测试试验中芯片结温和有限元仿真结果误差均小于5%.因此,提出的修正结环境热阻矩阵的方法可以快速且便捷地预测不同功率芯片的结温,并对器件的散热性能进行较为准确的预估.     

大功率LED多芯片集成封装的热分析

随着高亮度白光LED在室内、室外照明领域的应用,多芯片LED的集成封装方式是其发展的主要趋势之一,而热问题却是多芯片LED集成封装的瓶颈问题之一。建立了多芯片LED集成封装的等效热路模型,并采用有限元分析(FEA)的方法对多芯片LED集成封装的稳态热场分布进行了分析,同时通过制作实际样品研究大功率LED多芯片集成封装的热阻、发光效率与芯片工作数量的关系。结果表明集成封装的多芯片白光LED结温随着集成芯片数量的增加成线性增长,芯片到基板底面的热阻随着芯片工作数量的增加而增大,而其发光效率随着集成芯片数量的增加成线性减小。     

高压倒装LED照明组件的热性能

高压(HX)倒装LED是一种新型的光源器件,在小尺寸、高功率密度发光光源领域有广泛的应用前景.设计了4种不同工作电压的高压倒装LED芯片,进行了流片验证,并对其进行了免封装芯片(PFC)结构的封装实验,在其基础上研制出一种基于高压倒装芯片的PFC-LED照明组件.建立了9V高压倒装LED芯片、PFC封装器件及照明组件的模型,利用流体力学分析软件进行了热学模拟和优化设计;利用T3Ster热阻测试分析仪进行了热阻测试,验证了设计的可行性.结果表明,基于9V高压倒装LED芯片的PFC封装器件的热阻约为0.342 K/W,远小于普通正装LED器件的热阻.实验结果为基于高压倒装LED芯片的封装及应用提供了热学设计依据.     

微波芯片倒装金凸点热疲劳可靠性分析及优化

为了满足射频系统小型化的需求,提出了一种基于硅基板的微波芯片倒装封装结构,解决了微波芯片倒装背金接地的问题.使用球栅阵列(BGA)封装分布为周边型排列的GaAs微波芯片建立了三维有限元封装模型,研究了微波芯片倒装封装结构在-55～125℃热循环加载下金凸点上的等效总应变分布规律,同时研究了封装尺寸因素对于金凸点可靠性的影响.通过正交试验设计,研究了凸点高度、凸点直径以及焊料片厚度对凸点可靠性的影响程度.结果表明:金凸点离芯片中心越近,其可靠性越差.上述各结构尺寸因素对凸点可靠性影响程度的主次顺序为:焊料片厚度＞金凸点直径＞金凸点高度.因此,在进行微波芯片倒装封装结构设计时,应尽可能选择较薄的共晶焊料片来保证金凸点的热疲劳可靠性.     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件(3D-MCM).采用层压、开槽等工艺获得埋置式高密度多层有机(FR-4)基板,通过板上芯片(COB)、板上倒装芯片(FCOB)、球栅阵列(BGA)等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术(SMT)兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成r融合多种互连方式3D-MCM封装结构.埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题.对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性.电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

硅基线性模式APD焦平面研制

针对三维激光雷达的应用场景对雪崩光电二极管(APD)焦平面的性能要求,研究并制备了一种2×128硅基线性模式APD焦平面组件,它由硅基APD焦平面阵列、读出电路和制冷封装管壳组成。APD像元采用拉通型结构,通过大尺寸微透镜实现了高填充因子,通过隔离环掺杂实现了串扰抑制。通过离子注入工艺实现了击穿电压和响应电流的均匀性。设计大带宽低噪声跨阻放大电路、高精度计时电路,实现了窄脉宽、高灵敏度探测。采用气密性封装,实现了APD焦平面制冷一体化封装,制冷温差在40 K以上。测试结果表明,焦平面的探测阈值光功率可达3.24 nW,响应非均匀性为3.8%,串扰为0.14%,最小时间分辨率可达0.25 ns,实现了强度信息与时间信息同时输出的功能。     

Development of 3-D Stack Package Using Silicon Interposer for High-Power Application

Stacking of many functional chips in a 3-D stack package leads to high heat dissipation. Therefore, a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3-D stacked package with silicon interposers was developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer were formed by through silicon via. Silicon interposer has much high thermal conductivity than organic interposer, therefore the package thermal resistance is lower. Thermal performances of the 3-D package were analyzed and thermal enhancements like thermal via, thermal bridging were evaluated. The designed package showed 5 times lesser thermal resistance compared to a similar package with organic substrate. An additional silicon heat spreader was designed and attached to the package for high power application. Thermal analysis was performed to optimize package thermal performances and experimental validation was carried out. The designed 3-D stack package is suitable for 20 W application.     

Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing

This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper.     

GaN HEMT器件热特性的电学测试法

基于JEDEC颁布的结到壳热阻瞬态热测试界面法,对测试GaN HEMT器件热特性的电学法进行了研究.通过合理的测试电路设计,有效解决了GaN HEMT器件电学法测试中的栅极保护问题和自激问题,实现了GaN HEMT器件的界面热阻测量.根据测得的热阻-热容结构函数曲线可知,GaN HEMT器件结到壳热阻主要由金锡焊接工艺和管壳热特性决定.结合结构函数分析,对金锡焊接部分热阻和管壳热阻进行排序可剔除有工艺缺陷的器件.与红外热成像法的结温测试结果进行对比分析,证实了电学法测试结果的准确性.     

深低温大功率电阻阵列封装结构研究

电阻阵列的封装需求向着集成度高、大功率、深低温方向发展。为了满足130 K以下低温工作、稳态功率100 W以上的深低温应用需求，提出了一种利用液氮进行制冷的集成封装结构，并利用有限元仿真和实测验证相结合的方法验证了装置的制冷能力。结果表明，热沉钼与陶瓷电极板的厚度均为2 mm的情况下，加热功率在0.1~192.76 W区间内，有限元仿真得到的温度与实测温度最大误差小于7.67%，引起误差的主要原因是封装结构件的体热阻及界面热阻随温度发生变化而仿真时采用恒定热阻。结构能够在加热功率小于211.90 W的工况下正常工作。在设计的100 W稳定加热工况下，芯片衬底温度不高于101.9 K，热应力为5.66 MPa，满足设计要求。     

MCM-D技术电热特性综述

本文主要说明了淀积型多芯片组件(MCM-D)技术所使用的主要材料的热特性。此技术采用倒装片技术把硅芯片安装到硅基板上。阐述了薄膜电阻和接触电阻的测量与所使用金属的温度范围-28℃-100℃的比较。一套典型的试验结构诸如开尔文接触、横桥电阻(CBR)及Van der Pauw 结构不仅已用于此技术,而且为了测试通过球倒装片连接的接触电阻,采用一新的开尔文式结构。已获得MCM封装的热模型,并考虑由此类封装增加的所有的热电阻。     

带有TSV的硅基大功率LED封装技术研究

介绍了一种带有凹槽和硅通孔(through silicon via,TSV)的硅基制备以及晶圆级白光LED的封装方法。针对硅基大功率LED的封装结构建立了热传导模型,并通过有限元软件模拟分析了这种封装形式的散热效果。模拟结果显示,硅基封装满足LED芯片p-n结的温度要求。实验结合半导体制造工艺,在硅基板上完成了凹槽和通孔的制造,实现了LED芯片的有效封装。热阻测试仪测得硅基的热阻为1.068K/W。实验结果证明,这种方法有效实现了低热阻、低成本、高密度的LED芯片封装,是大功率LED封装发展的重要方向。     

Ultrasonic bonding for multi-chip packaging bonded with non-conductive film

System-on-Chip and System-on-Package technologies have advantages depending on application needs. As a number of electrical and electronic equipment manufacturers have an interest in increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will support next-generation high-end semiconductors such as high speed microprocessors and high speed memories. However, there are many issues regarding process integration, thermal management, and reliability of 3D stacked package.In this study, the printed circuit board (PCB), silicon carrier and silicon chip are integrated with ultrasonic vibration. Die shear tests of the joints were carried out with increasing bonding time and input power to optimize the bonding condition. The integrated chips were successfully bonded to the PCB with and without NCF using a transverse ultrasonic bonding. Electrical resistance of multi-chip bonded with NCF (10 mΩ) measures lower than that bonded without NCF (28.9 mΩ). The voids and delamination were easily found on the joint bonded without NCF that caused lower shear strength.     

Evaluation of Thermal Resistance Matrix Method for an Embedded Power Electronic Module

Thermal characterization provides data on the thermal performance of electronic components under given cooling conditions. The most common thermal characterization parameter used to characterize the behavior of electronic components is the thermal resistance. In this work, experiments are conducted to obtain thermal characterization data for different chips in a multichip package. Using this data, it is shown that the assumption of a linear temperature rise with input power is valid within the expected range of operation of the electronic module. Secondly, the applicability of a resistance matrix superposition methodology to the packaging structure of an integrated power electronic module is evaluated. The temperatures and the associated uncertainties involved in using the resistance matrix superposition method are compared to those obtained directly by powering all chips. It is shown that for any arbitrary power losses from the chips, the resistance matrix superposition method can predict the temperatures of a multichip package with reasonable accuracy for temperature rise up to 50degC.     

Investigations of thermal crosstalk in laser arrays for WDMapplications

Our studies on the thermal crosstalk of laser arrays with integrated thin-film heaters involved theoretical as well as experimental investigations. Comparing the effects of intentional geometrical variations of the device design, we found that the relative thermal crosstalk depends critically on the distance between the active area and the film heater. The most striking result is that a minimization of the thermal resistivity of the device does not always lead to a reduced thermal crosstalk. We demonstrate that an additional heat barrier close to the active region and/or an improved heat transfer between the submount and the heat sink may reduce the relative thermal crosstalk, a result completely unexpected from intuitive considerations