PCIE2．0的超远距离传输实现

PCIE2．0作为用于芯片间和板间互连的、高性能、点对点、基于报文互换的新型I／O互连技术,已被公认为行业的标准,在计算机系统中得到了广泛应用。PCIE2．0在物理层采用基于SERDES的串行通信技术,数据传输速率可达5Gbps,最多支持32通道。随着信号频率的增加,信号完整性问题变得日益突出,衰减、串扰和抖动的共同作用导致信号严重失真,传输距离受到限制。采用一种高效能的中继芯片,对PCIE2．0总线高速串行信号进行中继,实现了远距离传输,并在、实际系统中得到了验证。     

高速突发模式误码测试仪的FPGA实现方案

突发模式误码测试仪与一般连续误码测试仪不同,其接收端在误码比对前要实现在十几位内,对具有相位跳变特点的信号进行时钟提取和数据恢复,并且在误码比对时须滤除前导码和定界符,仅对有效数据进行误码统计。本文提出一种基于FPGA实现的高速突发模式误码测试仪设计方案,并介绍该方案的总体设计过程,以及FPGA中主要功能逻辑模块的工作原理和控制系统的设计。该测试仪应用于1.25GHz GPON系统突发式光接收模块的误码测试中,具有较好的性能和实际意义。     

Identification with stochastic sampling time jitter

This work investigates how stochastic sampling jitter noise affects the result of system identification, and proposes a modification of known approaches to mitigate the effects of sampling jitter, when the jitter is unknown and not directly measurable. By just assuming conventional additive measurement noise, the analysis shows that the identified model will get a bias in the transfer function amplitude that increases for higher frequencies. A frequency domain approach with a continuous-time model allows an analysis framework for sampling jitter noise. The bias and covariance in the frequency domain model are derived. These are used in bias compensated (weighted) least squares algorithms, and by asymptotic arguments this leads to a maximum likelihood algorithm. Continuous-time output error models are used for numerical illustrations.     

基于数据转换跟踪环的时钟抖动测试算法

提出基于数据转换跟踪环的光通信时钟抖动的测试算法。根据抖动测试模型推导得到等效基带相位模型,给出抖动测试误差幅度的表达式,说明抖动测试幅度与环路滤波器增益、抖动源幅度和抖动源频率有关。FPGA定点仿真表明,抖动测试误差幅度的仿真与理论结果一致。该算法为光通信中的抖动测试提供了一个简单、精确的方法。     

Bidirectional differential on-chip wave-pipelined serial interconnect with surfing

In the literature, surfing technique has been proposed for differential on-chip wave-pipelined serial interconnects with uniform repeaters (UR) and non-uniform repeaters to increase the data transfer rate for unidirectional schemes. In this paper, a novel bidirectional data transfer through the differential wave-pipelined serial interconnects with surfing for UR is proposed. A new circuit called ‘Bidirectional surfing inverter pair’ is proposed for differential wave-pipelined serial interconnects. The method of logical effort is used for the design of surfing circuits. To evaluate the efficiency of these techniques, 40 mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver and delay locked loop in UMC 180 nm technology and their performances are studied through post layout simulations. The proposed bidirectional differential surfing scheme has a maximum data transfer rate of 2 Gb/s and has allowable jitter of 52 ps on both directions through the same interconnects.     

一种具有不平等差错保护能力的TURBO码

根据Turbo码编码器的组成及码序列交织的原理,使用具有Smile属性的Helical交织器,研究了在同一块数据内部不同位置具有不平等差错保护能力的4状态1／3码率TURBO码,分析了不平等差错保护能力的分布规律和产生原因,给出了在高斯白噪声信道下的误码率。通过合理地使用具有较高差错保护能力的信息位可以使通信系统的性能得到提高。     

Transmitter equalization for 4-Gbps signaling

Most digital systems today use full-swing, unterminated signaling methods that are unsuited for data rates over 100 MHz on 1-meter wires. We are currently developing 0.5-micron CMOS transmitter and receiver circuits that use active equalization to overcome the frequency-dependent attenuation of copper lines. The circuits will operate at 4 Gbps over up to 6 meters of 24AWG twisted pair or up to 1 meter of 5-mil 0.5-oz. PC trace. In addition to frequency-dependent attenuation, timing uncertainty (skew and jitter) and receiver bandwidth are also major obstacles to high-data rates. To address all of these issues, we've given our system the following characteristics: An active transmitter equalizer compensates for the frequency-dependent attenuation of the transmission line. The system performs closed-loop clock recovery independently for each signal line in a manner that cancels all clock and data skew and the low-frequency components of clock jitter. The delay line that generates the transmit and receive clocks (a 400-MHz clock with 10 equally spaced phases) uses several circuit techniques to achieve a total simulated jitter of less than 20 ps in the presence of supply and substrate noise. A clocked receive amplifier with a 50-ps aperture time senses the signal during the center of the eye at the receiver     

本振相位噪声对干涉式综合孔径辐射计性能的影响

从两路接收信号的相关系数方面分析相位噪声对毫米波综合孔径辐射计的影响。利用非线性方法对本振信号的相位噪声建立的模型进行仿真。研究了在相关系数幅度和相位不同的允许误差范围内对本振相位噪声的指标要求。     

硬盘读写通道的FIR噪声预测算法与仿真模型

本文提出了一种嵌入FIR噪声预测的部分响应最大似然算法（NPML—Noise-prediction Partial-response Maximum Likelihood），该算法改进了传统部分响应最大似然算法（PRML-Partial Response Maximum Likelihood）中Viterbi译码过程的分支度量计算方法，能白化信号中有色噪声，减少误码率，提高硬盘读写通道的性能。本文还建立了读写通道的图形化仿真模型，提出了FIR滤波器长系数的快速逼近方法，并构造了检验模型工作正确性的方法。通过仿真模型对传统的Viterbi译码算法与嵌入FIR预测的NPML算法进行了分析。结果表明，在相同的存储密度下，NPML能获得比PRML高xxdb的信噪比和低xxdb的位错误率。     

16 bit量化误差对正弦参数拟合影响的误差界

为了定量评估量化采样序列对四参数正弦拟合结果影响的误差规律,针对16 bit量化对四参数正弦拟合带来的影响,分别在有效位数、幅度、频率、初始相位和直流分量五项参数上进行了拟合误差界的搜索。选取的条件变量分别是幅度、序列所含波形的周波数、初始相位、直流分量以及序列数据点数。以两两联动的双条件组合方式进行误差界搜索,获得了各项参数的误差界随不同条件变化而变化的曲线规律,筛分出了显著影响量和不显著影响量,以及明确的误差上界和下界。以往的研究仅使用正态随机噪声方式表征其谐波失真以外的误差要素,本文揭示了量化误差影响的周期性特征,并以曲线包络方式给出了量化误差影响的误差界。量化误差对四参数拟合影响的误差界,可用于不确定度估计,以及测量条件选择。     

Bit error rate reduction for circular ultrawideband antenna by dynamic differential evolution

The dynamic differential evolution (DDE) is used to synthesize the radiation pattern of the directional circular arc array to minimize the bit error rate (BER) performance in indoor ultrawideband (UWB) communication system. Using the impulse response of multipath channel, the BER performance of the synthesized antenna pattern on binary pulse amplitude modulation system can be calculated. Based on the topography of the circular antenna array and the BER formula, the array pattern synthesis problem can be reformulated into an optimization problem and solved by the DDE algorithm. The novelties of our approach are not only choosing BER as the object function instead of sidelobe level of the antenna pattern but also considering the antenna feed length effect of each array element. The strong point of the DDE algorithm is that it can find out the solution even if the performance index cannot be formulated by simple equations. Simulation results show that the synthesized antenna array pattern is effective to focus maximum gain to the line of site path which scales as the number of array elements. In other words, the receiver can increase the received signal energy to noise ratio. The synthesized array pattern also can mitigate severe multipath fading in complex propagation environment. As a result, the BER can be reduced substantially in indoor UWB communication system. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012.     

Method for measuring jitter in VDUs

A method for measuring jitter in visual display units (VDUs) is proposed. The method is based on the fact that jitter is revealed by a variation in pulse amplitudes when the electron beam traverses in paths which are displaced in relation to each other. The obtained data demonstrate that frequency characteristics of jitter are of the white noise type. The pulse amplitude properties on the other hand appear to provide a promising basis for measuring jitter in VDUs.     

用于体全息存储系统的纠错编码及数据交错技术

体全息存储系统具有存储容量大、数据传输率高、存取时间短和可快速进行图像匹配及内容相关寻址操作等特点 .但要成为特性优良的通用型信息存储系统 ,就必须以可接受的误码率同时满足这些性能指标 (计算机外存储器的基本要求是使用户误码率低于 10 - 12 ) .如此 ,仅靠光学设计不是高性价比方法 .设计恰当的纠错编码和数据交错技术可以减轻对原始误码率的要求 ,缓解对系统设计、部件质量等方面的要求 ,在不牺牲其它系统目标的情况下 ,使 10 - 5的原始误码率达到 10 - 12的最终误码率水平 .研究了体全息存储通道中的噪声源及适用于体全息存储系统的纠错编码和数据交错技术     

PCI Express中2.5Gbps高速SerDes的设计与实现

PCI Express是当前广泛应用的高速串行传输标准,其V1.0版本提供2.5Gbps的高速传输带宽。对于高速串行传输而言,精确的发送定时与接收同步是其关键技术。本文在详细分析PCI Express物理层技术的基础上,特别针对串行接收端的数据时钟恢复CDR技术展开研究,采用基于锁相环结构的数据时钟恢复技术设计了一款2.5Gbps速率的高速物理层电路,并基于0.13μm CMOS工艺设计了版图实现。基于HSPICE的模拟结果表明,此设计完全满足了PCI Express的要求,其抖动的均方根值为1.51ps,峰峰值为8.14ps。     

结合天线选择的空间调制及性能仿真

提出了一种分组映射空间调制方案。每个时隙中有多个发射天线被同时激活,结合幅度相位调制技术,每根选中的天线发射不同的符号,并且所激活的特定天线序列也携带相应信息。相对传统空间调制技术而言,该方案可以有效地提高空间调制系统的频带利用率和传输速率。Rayleigh衰落信道的仿真结果表明,所提方案的误比特率（Bit Error Rate,BER）性能优于传统的空间调制与多输入多输出（Multi-Input Multi-Output,MIMO）技术。方案可进一步结合发射天线选择（Antenna Selection,AS）技术,提高系统的传输质量。实际多极化MIMO信道的测量和仿真结果表明,在发端天线选择数目均相同时,分组映射调制的性能明显优于空间调制,结合AS的调制系统性能明显优于未结合AS的系统。     

Hybrid weighted bit flipping low density parity check decoding

Low density parity check codes (LDPC) exhibit near capacity performance in terms of error correction. Large hardware costs, limited flexibility in terms of code length/code rate and considerable power consumption limit the use of belief-propagation algorithm based LDPC decoders in area and energy sensitive mobile environment. Serial bit flipping algorithms offer a trade-off between resource utilization and error correction performance at the expense of increased number of decoding iterations required for convergence. Parallel weighted bit flipping decoding and its variants aim at reducing the decoding iteration and time by flipping the potential erroneous bits in parallel. However, in most of the existing parallel decoding methods, the flipping threshold requires complex computations.In this paper, Hybrid Weighted Bit Flipping (HWBF) decoding is proposed to allow multiple bit flipping in each decoding iteration. To compute the number of bits that can be flipped in parallel, a criterion for determining the relationship between the erroneous bits in received code word is proposed. Using the proposed relation the proposed scheme can detect and correct a maximum of 3 erreneous hard decision bits in an iteration. The simulation results show that as compared to existing serial bit flipping decoding methods, the number of iterations required for convergence is reduced by 45% and the decoding time is reduced by 40%, by the use of proposed HWBF decoding. As compared to existing parallel bit flipping decoding methods, the proposed HWBF decoding can achieve similar bit error rate (BER) with same number of iterations and lesser computational complexity. Due to reduced number of decoding iterations, less computational complexity and reduced decoding time, the proposed HWBF decoding can be useful in energy sensitive mobile platforms.     

2GHz的超高速数据采集系统设计与实现

针对合成孔径雷达对超高速率效据采集系统的需要,研制了一款采样率高达2GHz的数据采集系统。该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存,采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。测试结果表明该系统在2GHz采样率时有效位数大于6比特,实现了在高速采样的同时达到较高分辨率的要求。     

Source-synchronous testing of multilane PCI Express and HyperTransport buses

This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses. This approach is suitable for integration with existing ATE and can provide more than 100 independent differential-pair signals. We describe a specific application with 32 lanes of PCI Express, running at 2.5 gigabits per second (Gbps) per lane, and 32 data channels of HyperTransport, at 1.6 Gbps per channel. The differential source-synchronous nature of these buses presents difficulties for traditional (single-ended, synchronous) ATE. We solve these problems by using true-differential driver and receiver test modules tailored for the specific I/O protocols. We satisfy a further requirement for jitter tolerance testing by incorporating a novel digitally synthesized jitter injection technique in the driver modules. The modular nature of our approach permits customization of the test system hardware and optimization for specific DUT test requirements.     

Bit‐depth extension: Overcoming LCD‐driver limitations by using models of the equivalent input noise of the visual system

Abstract— Continuous tone, or “contone,” imagery usually has 24 bits/pixel as a minimum, with 8 bits each for the three primaries in typical displays. However, lower‐cost displays constrain this number because of various system limitations. Conversely, higher‐quality displays seek to achieve 9–10 bits/pixel/color, though there may be system bottlenecks limited to 8. The two main artifacts from reduced bit‐depth are contouring and loss of amplitude detail; these can be prevented by dithering the image prior to these bit‐depth losses. Our technique builds on Roberts's noise‐modulation idea and the subsequently influenced work in halftoning for hardcopy and dithering for displays. However, most halftoning/dithering work was primarily directed to displays at the lower end of bits/pixel (e.g., 1 bit as in halftoning) and higher ppi. We approach the problem from the higher end of bits/pixel/color, for example, 6–8, and lower spatial resolution (<100 ppi), which changes the game substantially from halftoning experience. Instead of spatial dither, it is better to use an amplitude dither. In addition, dynamic displays allow for the use of a temporal dithering component. This paper will report on techniques and observations made in achieving contone quality on ～100‐or‐less‐ppi LCDs starting from 4‐ to 8‐bit driver limits, and resulting with no visible dither patterns, noise, contours, or loss of amplitude detail at viewing distances as close as the near focus limit (～120 mm).     

Performance of multiple access CSK communication system with DF cooperative strategy

A multiple access chaos shift keying cooperative communication (MA-CSK-CC) system over Rayleigh fading channels and in the presence of Gaussian white noise is investigated in depth in this paper. The simplified half-duplex with a single relay decode-and-forward (DF) cooperative strategy is proposed to illustrate and analysis as an example. Exact and approximation bit-error-ratio (BER) performance expressions are derived. Simulation results demonstrate that the proposed system has a prominent advantage of high BER performance over the conventional multiple access CSK systems that have a single path to transmit signal at the same data rate over Rayleigh fading channels with additive Gaussian white noise. Moreover, based on the BER performance analysis, some useful results are also derived such as the relationships between BER versus spread spectrum factors, BER versus the number of users, etc.