MCA-newton method for circuit yield estimation and optimization

 An algorithm for circuits yield estimation and optimization is described.To obtain the first and second derivatives of yield with respect to center and obtain maximum production yield,Monte Carlo analysis (MCA)and Newton method are employed.By using“fail”samples and rearrange frequences in order of nonincreasing weights,the estimator is improved and the number of circuit analysis is reduced.Both theoretical analysis and calculation examples show that the estimator is correct and the proposed algorithm performs well and can be used for middle-scale circuit design.No matter the region of acceptability is convex ononconvex,the circuit is linear or nonlinear,the algorithm is available.     

基于RSM和均匀试验的IC成品率设计方法

本文给出了一种基于均匀试验设计的响应表面模型，同时得到该模型在VLSI集成电路参数成品率中的优化方法。本方法首先对电路的关键参数进行扫描，确定满足电路基本性能时的参数变化范围。在此范围内，可对电路参数进行以数论方法为基础的均匀试验设计和建立响应表面。对拟合得到的响应表面模型进行CV拟合检验，求出最佳的电路设汁值。本方法适用于集成电路的工艺、器件和电路级的模拟。     

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented     

AVS运动补偿电路的VLSI设计与实现

提出了一种基于AVS标准的高效的运动补偿电路硬件结构,该设计采用了8×8块级流水线操作,运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优利用。采用Verilog语言完成了VLSI设计,并通过EDA软件给出仿真和综合结果。     

一种新型三极管取样门电路设计

超宽探地雷达在无损检测系统中应用越来越广泛,采样电路是整个无损系统设计的关键。基于等效采样原理设计出一款新的三极管取样门电路。该电路克服了现有二极管取样门电路的缺点,很好地实现采样保持。利用先进设计系统(ADS)软件对该取样门电路进行仿真,输入脉冲重复频率为10 MHz的2 ns三角波信号,采样时钟重复频率为10 MHz且与被采样信号有100 ps延时差。对其进行采样,经过该取样门电路后,输出信号为2 μs。在聚四氟乙烯板上实现该电路,利用信号发生器输入一个90 ns的正弦波作为被采样信号,采样时钟为100 ns,经过该取样门电路后,输出信号周期为1 μs。实测与理论结果都表明该电路可以降低输入信号的频率,实现利用低速A/D对高速信号的数据采集,大大降低了整个系统的成本。     

Parasitic-aware RF circuit design and optimization

RF circuit synthesis techniques based on particle swarm optimization and adaptive simulated annealing with tunneling are described, and comparisons of parasitic-aware designs of an RF distributed amplifier and a nonlinear power amplifier are presented. Synthesized in 0.35-/spl mu/m digital CMOS using a single 3.3-V power supply, the designs provide an 8-dB gain and 8-GHz bandwidth for a four-stage distributed amplifier, and 1.2-W output power with 55% drain efficiency at 900 MHz for a three-stage power amplifier. A standard circuit simulator, HSPICE or SPECTRE, embedded in an optimization loop is used to evaluate cost functions. The proposed design and optimization methodology is computationally efficient and robust in searching complex multidimensional design spaces.     

Acceptance sampling: an efficient, accurate method for estimatingand optimizing parametric yield [IC manufacture]

Acceptance sampling is a new yield estimation and optimization method which combines the accuracy of Monte Carlo analysis with the computational efficiency of response surface methods. Response surface approximations are used to guide selection of simulation samples. Formulas based on established statistical methods (viz., confidence intervals, stratified sampling) estimate yield and predict accuracy. Yield optimization procedures employ conventional search algorithms. Examples using 50 to 100 simulations demonstrate accuracy matching 1000 to 10000 Monte Carlo samples     

Efficient implementation of uniform filter banks in the absence of critical sampling

It is shown that non-critically-sampled uniform filter banks have an efficient implementation, consisting of an FFT processor, and a time-varying structure derived from the prototype filter polyphase network. It is also shown how DFT filter bank optimisation techniques can be applied in the general case.<>     

配电线路路径优化设计及选择

配电线路路径的优化设计和选择问题,直接影响到配电线路供电的效率、效益.基于此,本文对配电线路路径优化设计及选择问题展开具体分析.     

Efficient SRAM yield optimization with mixture surrogate modeling

Largely repeated cells such as SRAM cells usually require extremely low failure-rate to ensure a moderate chi yield. Though fast Monte Carlo methods such as importance sampling and its variants can be used for yield estimation, they are still very expensive if one needs to perform optimization based on such estimations. Typically the process of yield calculation requires a lot of SPICE simulation. The circuit SPICE simulation analysis accounted for the largest proportion of time in the process yield calculation. In the paper, a new method is proposed to address this issue. The key idea is to establish an efficient mixture surrogate model. The surrogate model is based on the design variables and process variables. This model construction method is based on the SPICE simulation to get a certain amount of sample points, these points are trained for mixture surrogate model by the lasso algorithm. Experimental results show that the proposed model is able to calculate accurate yield successfully and it brings significant speed ups to the calculation of failure rate. Based on the model, we made a further accelerated algorithm to further enhance the speed of the yield calculation. It is suitable for high-dimensional process variables and multi-performance applications.     

Analog circuit design optimization through the particle swarm optimization technique

This paper details the Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. It is shown the practical suitability of PSO to solve both mono-objective and multiobjective discrete optimization problems. Two application examples are presented: maximizing the voltage gain of a low noise amplifier for the UMTS standard and computing the Pareto front of a bi-objective problem, maximizing the high current cut off frequency and minimizing the parasitic input resistance of a second generation current conveyor. The aptness of PSO to optimize difficult circuit problems, in terms of numbers of parameters and constraints, is shown.     

一种基于省时考虑的深亚微米VLSI的物理验证方法

现代VLSI开发的后端设计人员面临巨大的产品上市时间压力,尤其是对物理验证的过程而言时间更是紧张。本文结合工程经验阐述了物理验证的步骤和原理,结合Synopsys公司的物理验证工具Hercules的特点,提出了一种比较省时的物理验证流程,已用于实际数字调制芯片设计并流片。     

基于VLSI设计实现的高效颜色插补算法

针对Bayer格式阵列的CMOS图像传感器(CIS)片上系统(SoC)中图像信号处理单元(ISP)的研究,提出一种适合VLSI实现的高效颜色插补算法。算法重点重建了缺失的G分量,先进行像素边缘判断,进而结合边缘方向梯度加权计算,使得G分量的重建有效避免了传统方法中易造成边缘变模糊的现象;对于B和R分量的重建,充分利用小范围内已知的像素分量值对其进行线性插补,使得插补后的值更接近真实值。通过对色彩测试标板和自然图像的模拟实验表明,该算法插补后的图像与传统算法相比更清晰、信噪比更高。算法基于VL-SI设计实现,并通过FPGA验证,结果表明,该算法易于片上实现,耗费资源892个LE,最大频率可达142MHz,完全满足实时处理需求。     

A simple method of photomask yield optimization by defect inspection

The quality of the photomask set decides to a large extent the quality and quantity of the device that will be produced. In order to ensure the quality of the photomasks, several sophisticated instruments are commercially available. However, in a research type of environment, the cost of such equipment can be prohibitive. In this paper, we propose a simple method of multiple master mask preparation with subsequent matching of defective die locations to optimize the master mask set. The advantage here is that a very good master mask set can be chosen so that minimum number of dies on the photomask set itself contribute to low wafer yield. The method is based on manual inspection of individual dies on photomasks and can be practically used for a complexity of up to 500 components.     

A modular neural network approach to microelectronic circuit yield optimization

The unpredictable variation in microelectronic circuits due to process tolerances increases significantly with increased levels of miniaturization. If ignored, the variation will result in poor manufacturing yield. If a worst-case approach is adopted, a loss of competitive edge results. This situation provides the motivation for efficient robust design of VLSI circuits, the subject of this paper. Given the need for efficiency of analysis without significant loss of accuracy, a method is proposed which generates a neural network for mapping process-level parameters to circuit performance. The approach uses a modular neural network—an adaptive mixture of local experts competing to learn different aspects of a problem. Once the neural network model is established and validated, it is employed in performing extremely efficient optimization of the circuit yield at minimal cost: the trained ANN acts as a cheap but accurate simulator which when supplied with a set of inputs which characterize transistors at the process and device level calculates the circuit performance with 97% accuracy at 1% of the cost of a full SPICE simulation. Even when the cost of ANN training is factored in, average cost savings of 80% are achieved during yield optimization. The neural net approach offers significant advantages including vastly reduced computational cost with little loss of accuracy and complete generality of application.     

Efficient method for simulating time delays of distributedinterconnections in VLSI circuits

A new technique is described for modelling a general distributed RC line through a simple lumped net. This reduced order model approximates both the long time voltage response and the input loading effect of the line. The proposed method has the advantage of allowing the employment of circuit simulators such as SPICE to evaluate interconnect delays in complex layouts     

一种带失调自校正运放的电流采样电路设计

本文介绍了一种应用在电源管理芯片中带失调自校正运放的电流采样电路设计。相对于传统的运放失调消除技术,本失调自校正运放设计无需开关电容相关技术,可节省一定的芯片面积,通过在芯片启动时自动校正输入失调,并将校正位锁存。之后,由于运放零失调,可大大提高所述电流采样电路的精度。该技术已经成功应用在数款电源管理芯片中,量产测试结果表明,采用该电路的电流采样精度小于0.2%。     

VHDL语言在电路设计中的优化

VHDL设计是行为级的设计。利用VHDL设计电路是目前对于较复杂的电路系统进行设计时的最好选择,但设计中如何进行电路的简化直接关系到电路的复杂度及可靠性。VHDL语言的优化设计旨在充分利用CPLD／FPGA所提供的硬件资源,使项目设计能适配到一定规模的CPLD／FPGA芯片中,并提高系统的工作速度、降低系统功耗。优化的主要目标是减少适配所需要的宏单元数。本文分析了VHDL设计中容易引起电路复杂化的原因,提出了相应的解决方法。