Threshold voltage characteristics of depletion-mode MOSFET's

This paper presents the results of a study of the characteristics of the depletion-mode MOSFET. In particular, it is shown that the threshold voltage of this device is a function of its mode of operation (linear or saturated) due to a change in dominant conduction mechanisms caused by the finite depth of donor impurities in the channel. The effect of these impurities on the short channel behavior of the devices also is examined.     

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO2) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Simulating single-event burnout of n-channel power MOSFET's

Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs     

Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET's using low-frequency (8-Hz)C-Vmeasurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time(t) and temperature(T) dependence for threshold-voltage shift (deltaV_{T}) is represented experimentally asdeltaV_{T}infin log (t/t_{0}), wheret_{0}^{-1} infin exp (-1.0 eV/kT). The positive VTshift appears faster for MOSFET's fabricated with dry O2oxides as gate insulator than for those with HCI oxides. It is also shown that the VTshift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.     

A study of photon emission from n-channel MOSFET's

It is known that an n-channel MOSFET, operating in the saturation region, is accompanied by visible light emission. The spectral distribution of this emitted light is reported in this paper for the first time. It behaves as exp (-α . hv) under various bias conditions (α: constant); the energy state of hot electrons is described as a Maxwell-Boltzmann distribution. The hot-electron temperature in an n-channel MOSFET is experimentally evaluated from the photon spectrum analysis. As compared with the electric field strength calculated by two-dimensional simulation, the hot-electron temperature is found to be determined as a function of the electric field strength in the drain avalanche region.     

A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects.     

Fabrication of inversion-type n-channel MOSFET's using cubic-SiC on Si

Inversion-type n-channel MOSFET's of cubic-SiC were successfully fabricated. Cubic-SiC was grown on Si     

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V _G-V_T values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1-μm range     

Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

We use the n-channel deep-depletion SOS/MOSFET to measure carrier velocity of electrons in thin SOS films. The data are presented as a function of electric field up to the point where the velocity saturates. We show the consistency of these data across devices of different gate lengths and manufacture operating at different gate voltages. These results lead to the concept of a "universal curve" for the carrier velocity versus electric field relationship which can be applied to the modeling of velocity-saturation effects in n-channel SOS/MOSFET's. We develop a technique for such an application. In addition, by compensating for the effect of surface scattering on mobility, we have been able to show that the velocity versus field relationship at the surface of thin SOS films agrees very closely to that obtained from bulk silicon.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Fully depleted SOI MOSFET's include an inherent parasitic lateral bipolar structure with a floating base. We present here the first complete physically based explanation of the bipolar gain mechanism, and its dependence on bias and technological parameters. A simple, one-dimensional physical model, with no fitting parameters, is constructed, and is shown to agree well with simulations and measurements performed on a new type of SOI MOSFET structure. It is shown that parameters which affect the gain, such as SOI layer thickness, body doping concentration and gate and drain voltages, do so primarily by affecting the concentration of holes in the body region. Thus, current gain falls dramatically with increasing drain voltage due to the associated impact ionization driven increase in the hole concentration. Gummel plots of this parasitic bipolar indicate an apparent ideality factor of 0.5 for the hole current, due to the body hole concentration's dependence on drain voltage     

Behavior of holes generated by impact ionization in n-channel MOSFET's

The behavior of holes, which are generated mainly by impact ionization, is described with the results obtained from a two-dimensional numerical analysis. The hole density has been found to be large even near the source for shorter channel lengths.     

Threshold voltage shift due to low energy electrons used in SEM voltage contrast testing

Scanning electron microscope (SEM) voltage contrast testing is being developed for functional design verification, failure analysis, and development of VLSI devices. This technique imparts little electrical loading and requires no physical contact to the chip, both of which are advantages for device testing via internal nodes. One area of concern, however, is the effect of the low-energy electrons (<5 keV) on the transistor parameters. Even for incident electrons below 8 keV which do not penetrate to the gate oxide, a threshold shift has been observed in SOS MOSFET's. The parameter shift is a result of damage to the gate oxide by secondary X-rays generated by the electrons. Limits on the electron energy and fluence are set to minimize the threshold shift during SEM testing. It is found that under the proper conditions sufficient time is available to perform both voltage contrast imaging and nodal waveform measurements without incurring serious threshold voltage shifts.     

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.