电子元器件封装技术发展趋势

晶圆级封装、多芯片封装、系统封装和三维叠层封装是近几年来迅速发展的新型封装方式,在推动更高性能、更低功耗、更低成本和更小形状因子的产品上,先进封装技术发挥着至关重要的作用。晶圆级芯片尺寸封装(WCSP)应用范围在不断扩展,无源器件、分立器件、RF和存储器的比例不断提高。随着芯片尺寸和引脚数目的增加,板级可靠性成为一大挑战。系统封装(SIP)已经开始集成MEMS器件、逻辑电路和特定应用电路。使用TSV的三维封装技术可以为MEMS器件与其他芯片的叠层提供解决方案。     

3D-TSV封装技术

3D-TSV封装技术是实现多功能、高性能、高可靠且更轻、更薄、更小的系统级封装最有效的技术途径之一。3D-TSV封装关键技术包括:通孔制作、通孔薄膜淀积、磁控溅射、通孔填充、铜化学机械研磨、超薄晶圆减薄、芯片/晶圆叠层键合等。阐述了每种关键技术的工艺原理、技术特点、应用范围及发展前景,关键设备、关键材料以及TSV在三维封装技术中的应用。     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

Applied NokotaTM电化学沉积系统助力先进芯片封装

应用材料公司日前宣布,面向晶圆级封装(WLP)产业推出Applied Nokota?电化学沉积(Electrochemical Deposition, ECD)系统,凭借优秀的电化学沉积性能、可靠性、晶圆保护能力、可扩展性,以及生产力,提供先进封装技术.在该系统的助力下,芯片制造商、外包装配和测试(OSAT)企业将可通过低成本、高效率的方式使用不同的晶圆级封装工艺,包括凸块/柱状、扇出、硅通孔(TSV)等等,满足日益增多的移动和高性能计算应用需求.     

新世纪电子器件封装技术展望

扼要分析了电子器件封装技术迅速发展的成因，预测了电子封装新技术的发展方向，深入阐述了引脚布置方式的突破，BGA技术的发展，BGA和倒装芯片结合的优势，CSP产业化的关键，在晶圆片上进行CSP封装的新工艺，以及倒装芯片和CSP封装的综合比校。     

Tessera专注微电子和成像与光学技术

Tessera公司创立于1990年,公司的微电子解决方案以芯片规模、3D与晶圆级的封装技术,以及高密度的衬底与静音散热技术,支持客户生产体积更小、功能更强     

Ultra CSP晶片级封装

取得专利的低成本小型封装随着市场对更小、更快和不太昂贵器件需要的增长，工业上正在寻找一种使产品从导线焊接封装转到直接进行芯片连接（DCA）的解决方案。在近几年间，芯片大小的封装（CSP）已经显现出在球栅阵列（BGA）和倒装片的空隙之间架起的桥梁。由于许多设计预先考虑向DCA转移，所以已经把倒装片引入到他们的CSP或BGA封装里了。Kulicke＆Soffa工业股份有限公司的K＆S倒装片分部已经超出了传统的封装和CSP封装的范围，而转到向Ultra CSP技术发展。这种UltraCSP技术是一种晶片级（Wafer Level）CSP方案，是利用一…     

晶圆片级芯片规模封装技术(WLCSP)

本文主要介绍了一种新型的 CSP 高级封装——晶圆片级芯片规模封装技术(WLCSP)及其特点,并简述了 CSP 封装的主要特点及发展前景。     

高可靠先进微系统封装技术综述

在人工智能、航空航天、国防武器装备电子系统小型化、模块化、智能化需求驱动下,系统级封装设计及关键工艺技术取得了革命性突破。新型的系统封装方法可把不同功能器件集成在一起,并实现了相互间高速通讯功能。封装工艺与晶圆制造工艺的全面融合,使封装可靠性、封装效率得到极大的提升,封装寄生效应得到有效抑制。文章概述了微系统封装结构及类型,阐述了高可靠晶圆级芯片封装(WLP)、倒装焊封装(BGA)、系统级封装(SIP)、三维叠层封装、TSV通孔结构的实现原理、关键工艺技术及发展趋势。     

圆片级封装技术

圆片级封装(Wafer-LevelPackaging,WLP)已成为先进封装技术的重要组成部分,圆片级封装能够为芯片封装带来批量加工的规模经济效益。在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。综述了圆片级封装的技术及其发展趋势。     

Wafer-level chip scale packaging: benefits for integrated passivedevices

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost     

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.     

A minimal CSP

A chip scale package (CSP) using wafer scale processing was developed for a line of low cost, small form factor integrated circuits. The package uses polymeric repassivation and electrodeposited solder bumps connected by a unique conductor patterning method. The finished package resembles a common chip resistor. Reliability testing was used to optimize the bump design and the assembly methodologies. Field performance of more than 20 million packages has validated the test results     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Encapsulation process development for flexible-circuit based chip scale packages

The ultimate driving forces for the development of small form-factor chip scale packages (CSPs) are the market demands for small, light and high performance products. The flex-based /spl mu/BGA technology has been a very successful package format, and tremendous efforts have been implemented in the process development for the technology. In this article, three flex-based chip scale packages (based on patented /spl mu/BGA technology) will be discussed. The focus will be on the encapsulation process development. Because of the unique package structures and material sets used in the flex-based CSPs, various encapsulation challenges were raised. The encapsulation solutions are compared and discussed for each type of flex-based /spl mu/BGA technologies, including the dispensing pump technologies, material characterization, process characterization and optimization. Based on the evaluation results, type C /spl mu/BGA technology is recommended for its simple assemble process flow, balanced protection on beam leads and solder ball joints and shorter manufacturing cycle time as well.     

An overview of solder bump shape prediction algorithms withvalidations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range     

BGA／CSP和倒装焊芯片面积阵列封装技术

随着表面安装技术的迅速发展,新的封装技术不断出现,面积阵列封装技术成了现代封装的热门话题,而BGA／CSP和倒装焊芯片（F1iPChip）是面积阵列封装主流类型。BGA／CSP和倒装焊芯片的出现,适应了表面安装技术的需要,解决了高密度、高性能、多功能及高I／O数应用的封装难题。本文介绍了BGA／CSP和倒装焊芯片的封装理论和技术优势及制造流程,并阐述了植球机的基本构成和工作原理。     

High reliability, high density, low cost packaging systems formatrix systems for matrix BGA and CSP by vacuum printing encapsulationsystems (VPES)

Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

BGA器件及其常见的形式

BGA器件不仅能够满足现在已有的其它组件所不能够提供的高性能、大量I/O数量的应用要求,也给如今的有引脚元器件提供了一种可靠的可替换方案。对于在组件体的底部位置安置有大量焊球阵列的BGA器件来说有四种主要的类型。表面阵列配置的组装技术将会成为电子组装业最主要的发展潮流。