InP/InGaAs double-heterojunction bipolar transistors for high-speedoptical receivers

We fabricated monolithically integrated pin/HBT photoreceivers using FPIGA (full-potential InGaAs) DHBT's with various collector thicknesses. An HBT figure-of-merit was deduced from the relationship between measured bandwidths of the preamplifiers and the f_T's and f_max's of the DHBT's. A phenomenological device model of the DHBT's is proposed to find the optimum collector thickness that gives the highest bandwidth of the photoreceivers. Finally, we discuss the feasibility of monolithically integrating a pin-PD, preamplifier, buffer amplifier, and D-type flip-flop with an operating speed of 40 Gbit/s     

Temperature dependent common emitter current gain andcollector-emitter offset voltage study in AlGaN/GaN heterojunctionbipolar transistors

We have demonstrated state-of-the-art performance of AlGaN/GaN heterojunction bipolar transistors (HBTs) with a common emitter (CE) current gain of 31 at 175 K and 11.3 at 295 K. The increase in collector current and CE current gain at lower temperature can be attributed to the reduced base-emitter interface recombination current. We also observed an increase of collector-emitter offset voltage with decrease of temperature. The increase of V_CEOFF at lower temperature is related to an increase of V_BE as the base bulk current is increased, or to the reduction of the ideality factor n_BE     

Burst and low-frequency generation-recombination noise in double-heterojunction bipolar transistors

The low-frequency noise in a double-heterojunction bipolar transistor (DHBT) consisted of burst noise and generation-recombination g-r noise. The current dependence of the base burst noise with floating collector was of the form IB³and the current dependence of the collector g-r noise with HF short circuited base was as IC^3/2. The centers involved in the noise generation had an activation energy of about 0.40 eV, with an indication of a second center of lower energy in the collector noise.     

Collector offset voltage of heterojunction bipolar transistorsgrown by molecular beam epitaxy

The collector-emitter offset voltages of InAlAs/InGaAs heterojunction bipolar transistors grown by molecular-beam epitaxy are discussed. Both the difference between emitter and collector areas and electrical asymmetry between emitter and collector junctions in these mesa-isolated transistors account for the offset voltages observed. Devices exhibited offset voltages in the range of 50-300 mV, depending on the structures and device sizes. Several electrical and geometrical factors affecting the offset voltage are discussed in detail     

Comparison of input offset voltage of differential amplifiers using bipolar transistors and field-effect transistors

A field-effect transistor (whether junction type or MOS type) has very high input impedance. For those who desire to achieve a higher input impedance, it is often asked `Why aren't FET pairs used as input stages and bipolar transistors used as output stages, since compatible FET and bipolar transistor monolithic structures have been developed?' This correspondence is a study of this question.     

Collector models for bipolar transistors

Using Ryder's formula for drift velocity vs. electric field, the d.c. field and carrier densities in the collector of a bipolar transistor are calculated analytically for all possible bias conditions. This is accomplished by modeling the majority carrier distribution. The results are compared with computer calculations and fairly close agreement is found. The analytic calculations are used to make a detailed division of the (J_c, V_cb) plane into injection, depletion and scattering-limited drift velocity (SLDV) areas. It turns out that the doping level N_d and the collector width W determine the nature of this division of the (J_c, V_cb) plane.     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

AlGaAs/GaAs bipolar transistors with a modulation-doped superlattice emitter

A new emitter-base concept for heterojunction bipolar transistors is proposed and demonstrated. The abrupt or graded emitter-base heterojunction drawbacks are circumvented by means of a modulation-doped stack of ternary compound alternating with binary compound layers. This stack provides efficient barriers to the hole current while preserving good diode characteristics. These concepts are demonstrated by experimental results on small-area devices with a common-emitter gain of ~40 and a collector-emitter voltage offset of ~80mV.     

High efficiency, low offset voltage InGaP/GaAs power heterostructure-emitter bipolar transistors with advanced thermal management

High efficiency, low offset voltage InGaP/GaAs power heterostructure-emitter bipolar transistors (HEBTs) have been demonstrated. The large signal performance of the HEBTs is characterized. Output power of 0.25 W with power added efficiency (PAE) of 63.5% at 1.9 GHz has been achieved from a 26-finger HEBT with total emitter area of 873.6 /spl mu/m/sup 2/. Output power of 1.0 W with PAE of 63% has been obtained from the composition of four above-mentioned power cells at the optimum conditions of impedance matching. The thermal performance of HEBT is presented and the results show better thermal management than conventional HBT. The experimental results demonstrate good power performance and capability of HEBTs.     

Early voltage in very-narrow-base bipolar transistors

It is shown that for VLSI devices with very narrow base widths (less than 0.1 μm), the velocity saturation effect gives a substantial increase in Early voltage and a corresponding beneficial increase in output resistance. The theory is discussed, and practical results are presented     

On the modeling of polysilicon emitter bipolar transistors

In this paper, an attempt is made to derive a general analytical formulation for the current gain and emitter transit time of a polysilicon emitter bipolar transistor (BJT), which includes all previous models as particular cases. Firstly, it is shown that the minority-carrier injection and storage in the polysilicon region can be simply described by effective values of the minority-carrier diffusion length and mobility. These quantities are precisely defined, and depend on the microscopic transport properties of polysilicon grains and grain boundaries. Secondly, a general expression for the effective recombination velocity relative to the poly/mono interface is derived, which includes, and in some cases extends, all previous approaches. This results in a simple and general formulation which avoids some unnecessary simplification present in nearly all previous treatments, and allows easy comparison of the different models for the poly/mono interface and a clear assessment of the relevance of each physical mechanism. Finally, minority-carrier injection and storage in the single-crystal region is addressed. The effect of oxide breakup on both current gain and emitter transit time is also considered, and different models are compared     

Calculation of the emitter efficiency of bipolar transistors

The emitter efficiency of a bipolar transistor is calculated taking heavy doping effects such as impurity band formation and band tailing into account. It is shown that in most cases these effects, rather than the minority carrier lifetime in the emitter are limiting the transistor current gain. This allows us to define an effective emitter impurity profile for use in current transport calculations. The influence of the emitter and base impurity profiles upon the gain is studied, and experimental results are presented showing that the knowledge of the impurity profiles is sufficient to predict the one-dimensional current gain.     

1/f voltage noise in silicon planar bipolar transistors

Measurements on silicon planar transistors in the frequency range 1 Hz?1 kHz have shown conclusively that 1/f noise is present on the equivalent input noise-voltage generator. In some samples of transistors, correlation between the 1/f components of voltage and current noise was detected. In one sample, an estimate of the correlation coefficient was made, the result being a coefficient of approximately ?0.1.     

Simulation of electrical characteristics of InP double-heterojunction bipolar transistors with InGaAsSb base

We study the effect of antimony (Sb) content in the InGaAsSb base layer of InP double-heterojunction bipolar transistors (DHBTs), under the condition of lattice match, by using a two-dimensional device simulator Medici. Careful calibration of physical parameters is first done to ensure that the simulation result matches data measured from a reference device. When the composition of Sb in the InGaAsSb base region is varied, the conduction band offset (ΔE_C), effective density of states in conduction band and valence band (N_C, N_V), bandgap energy (E_G), and intrinsic carrier concentration (n_i) are changed accordingly. These semiconductor material parameters are considered in the simulation to compare the electrical characteristics of the DHBT. In addition to the Sb composition, different materials of In_0.52Al_0.48As or InP in the emitter are simulated. The study on Sb content in the base and the heterostructure of E-B junction helps the development and optimization of InGaAsSb DHBTs.     

Early voltage in double heterojunction bipolar transistors

The Early voltage for abrupt double heterojunction bipolar transistors (DHBTs) has been calculated by using an effective junction velocity (S_c) at the base-collector heterojunction. S_c is obtained by self-consistently partitioning thermionic and quantum mechanical tunneling currents. Unlike single heterojunction bipolar transistors (SHBTs), the Early voltage varies very rapidly at low reverse bias and approaches the SHBT-limit at sufficiently high reverse bias. This is attributed to the presence of an energy barrier at the b-c heterojunction     

Collector capacitance and high-level injection effects in bipolar transistors

A simple model for the behavior of the collector capacitance of bipolar transistors has been developed with the aim of studying high-level injection phenomena in epitaxial collectors. The Collector capacitance (Cc) calculated from the results of a dynamic small-signal measurement. It is Observed that Ccincreases by more than an order of magnitude as the collector current is increased from a low value into the quasi-saturation regime at a fixed collector-emitter voltage of 1 V. The collector capacitance is composed of a transition capacitance, which is due to the presence of unneutralized charges in the collector region, and of a diffusion capacitance, which is due to the presence of neutralized charge in transit across the base and the collector regions. The transition capacitance is the dominant component at low-current levels. However, at high-current levels, the diffusion capacitance predominates if the one, dimensional "base-widening" model (Kirk effect) becomes operative and the total capacitance becomes very large. This capacitance is found to be about an order of magnitude larger than that expected if the two-dimensional "lateral-spreading" model were dominant. Good agreement is observed between the experimental data and the theoretical Ccestimates using the one-dimensional model. Thus it is concluded that the base-widening model controls the behavior of our devices at high levels of injection in the collector.     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

A new simple analytical emitter model for bipolar transistors

An accurate analytic evaluation of emitter injection into an arbitrarily doped emitter (including a polysilicon-contacted emitter) is presented taking into account position-dependent quantities such as bandgap narrowing, Auger recombination and mobility. Two newly defined dimensionless parameters are introduced that are very useful for emitter design. These parameters are proposed to replace the conventional emitter Gummel number which becomes less useful when appreciable recombination takes place in the emitter. Universal emitter design curves are presented for devices made in silicon, GaAs and InGaAsP or in any other semiconductor for which a newly introduced lifetime model holds good. Numerical simulations show the accuracy and usefulness of the analytical model developed.