基于MATLAB的串联系统可靠性整数优化

分析了串联系统冗余问题的有约束整数优化求解基本思路,并给出了优化模型。利用基于MATLAB的BNB20（）函数,对串联系统的冗余分配和可靠度分配进行了整数优化,提供了工程可靠性整数优化的设计方法。算例结果验证了该方法的有效性和适用性。     

CMOS多晶电容工艺误差分析及设计研究

研究分析了CMOS多晶电容的工艺误差,给出了氧化硅介质层厚度的梯度误差、边际效应等工艺因素对CMOS多晶电容的影响。基于单位电容的改进设计,给出了CMOS多晶电容阵列的共心设计方法。采用0．6μm CMOS DPDM工艺,实现了基于CMOS多晶电容阵列的开关电容带通滤波器,实验结果表明本文的CMOS多晶电容设计方法具有较高的精度,能直接用于亚微米及深亚微米集成电路设计。     

亚微米门阵列ASIC设计技术

本文主要论述亚微米CMOS门阵列的设计技术,包括建库技术,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等,最后给出了应用实例。     

基于FPGA的FIR滤波器高效实现

本文针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行研究,首先给出了将乘法转化为查表的DA算法,然后简要介绍整数的CSD表示和我们根据FPGA实现要求改进的最优表示;接着,本文讨论了在离散系数空间得到FIR滤波器系数最优解的混合整数规划方法;最后采用这一方法设计了最优表示离散系数FIR滤波器,通过FPGA仿真验证这一方法是可行的和高效的.     

一种基于基本结构的CMOS CAM单元的优化设计

本文对采用0．18μm CMOS工艺设计的CAM存储单元的结构、工作原理和性能进行了分析和优化，并给出HSPICE仿真的结果，从仿真波形可以看出优化的合理可行。此CAM已成功地应用于CPU的存储器中。     

电流模式CMOS OTA滤波器实现

本文提出了利用CMOS OTA综合连续时间电流模式滤波器的方法。应用信号流图模拟,系统地生成了二阶CMOS OTA电流滤波器。分析了OTA的非理想因素对滤波器高频性能的影响,并给出了简单的高频补偿方案。最后,给出了一个四阶巴特沃思低通滤波器的设计实例并经PSPICE仿真证实。     

WDM光网络中资源优化目标的分析

讨论了WDM光网络中的逻辑拓扑设计问题,基于混合整数线性规划模型,提出光网络逻辑拓扑设计的若干优化目标函数,并综合相关文献对其中的变化关系作了阐述。     

高频RFID标签芯片解调电路的设计

给出了高频RFID标签芯片解调电路的设计。设计工艺采用中芯国际（SMIC）2P3M 0．35μm混合信号CMOS技术，并给出了spectre仿真环境下的仿真结果。晶体管级仿真和版图后仿真结果表明所设计电路满足高频RFID标签芯片解调要求。     

UHF RFID标签芯片解调电路设计

提出了一种应用于UHF RFID无源标签芯片解调电路的设计方法,该方法结构简单,能适用于不同协议,并具有低功耗、高稳定度和高灵敏度等优点。文中给出了基于TSMC 0．18μm CMOS混合信号工艺的设计实现方法及其在spectre仿真环境下的仿真结果。并通过MPW项目进行了流片验证。     

H．264编码器中插值运算和整数变换的优化

首先分析了H．264编码器中运算密集的插值和整数变换过程；然后对其进行算法改进和优化，给出整数变换的全零预先判决方法；最后以整数变换为例，使用Intel的MMX技术优化运算密集模块。优化后，测试表明插值运算和整数变换模块运行速度有数倍提高。     

A Discrete Filled Function Method for the Design of FIR Filters With Signed-Powers-of-Two Coefficients

In this paper, we consider the optimal design of finite-impulse response (FIR) filters with coefficients expressed as sums of signed powers-of-two (SPT) terms, where the normalized peak ripple (NPR) is taken as the performance measure. This problem is formulated as a mixed-integer programming problem. Based on a transformation between two different integer spaces and the computation of the optimal scaling factor for a given set of coefficients, this mixed integer programming problem is transformed into an equivalent integer programming problem. Then, an efficient algorithm based on a discrete filled function is developed for solving this equivalent problem. For illustration, some numerical examples are solved.     

A transistor performance figure-of-merit including the effect ofgate resistance and its application to scaling to sub-0.25-μm CMOSlogic technologies

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-μm CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness     

Surrogate Constraints Algorithm for Reliability Optimization Problems with Multiple Constraints

This paper presents a surrogate constraints algorithm for solving nonlinear programming, nonlinear integer programming, and nonlinear mixed integer programming problems. The algorithm contains a new technique for generating a succession of vector values of surrogate multiplier (ie, surrogate problems). By using this technique, a computer can keep a polyhedron, which is a vector space of surrogate multipliers to be considered at a certain time, in its memory. Furthermore it can cut the polyhedron by a given hyperplane, and produce the remaining space as the next polyhedron. Simple examples are included.     

Improvement of light-load efficiency using width-switching scheme for CMOS transistors

This paper presents a derivation of the optimum width of transistors to minimize losses in monolithic CMOS buck converters. The high optimal width requires a tapered inverter chain gate driver. A technique called "width switching" is presented. It can be integrated with the inverter chain to maintain maximum converter efficiency over a wide power range, particularly at light load. Experimental results are presented from a chip containing CMOS transistors optimized for power levels between 50 mW and 200 mW. Challenges in implementing the width-switching scheme and other applications are also discussed.     

Two-dimensional device simulator for gate level characterization

A novel device simulator using a Newton-Raphson method for searching for the output terminal potential has been developed for composite structures with inverter function. We have found it impossible to determine the output potential and to characterize the transfer curve for such devices using conventional device simulators.The present simulator, however, can handle gate level device simulation, such as an inverter with a linear or a nonlinear load, and a CMOS inverter. Consequently, an inverter can be characterized exactly in steady and transient operation without circuit simulation. Thus device design with use of the present device simulator becomes more efficient. Specific examples are given to illustrate some comprehensive features of this simulator.     

基于最小化平均分组跳的波长路由环网逻辑拓扑设计

本文提出了用混合整数线性规则（ＭＩＬＰ）进行波长路由环网的逻辑拓扑设计。对于给定的通信流量矩阵,其目标函数是最小经平均分组跳。以双向环网为例,对于不同网络结构参数的情况,进行了计算分析并给出了数值结果。对双向环网和单向环网的网络性能进行了比较分析。     

基于混合整数规划模型的PON与WiMAX融合网络规划(英文)

This article analyzes the characteristics of PON and WiMAX convergence network planning.Based on user coverage ratio,WiMAX channel allocation,cell radius,carrier-to-noise ratio threshold,and bandwidth constraint,we propose a mixed integer programming model solved by a Branch-Band and Heuristic Search method.Finally,the simulation result is given and analyzed.The planning method based on a mixed integer programming model can save 20 percentage of the overall planning cost,compared with the greedy algorithm.T...     

Design of nonuniformly spaced linear-phase FIR filters using mixedinteger linear programming

An optimization problem for designing a nonuniformly spaced linear-phase FIR filter with minimal complexity is formulated and solved by mixed integer linear programming (MILP). Examples illustrate that the proposed method is useful for designing a wide range of filter types and can outperform subset selection-based design methods     

Back-gate forward bias method for low-voltage CMOS digital circuits

The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time     

Joint Optical Network Design, Routing and Wavelength Assignment by Integer Programming

We present a new mathematical model for all-optical network design, including sparse optical cross connects placement, traffic routing and wavelength assignment. The proposed linear integer program is refined by introducing valid inequalities, and a cutting plane procedure is described. The solution procedure is implemented using commercial mixed integer programming solvers and applied to some real instances of metropolitan and wide area networks. We present encouraging results that show the validity of the approach.