Viterbi译码器的FPGA实现

详细分析了(2,1,6)Viterbi译码器的实现结构,提出了基于模块化并行算法构建Viterbi译码器,并利用Verilog在XilinxISE6.2中进行了建模仿真和综合,实验结果表明采用该结构体系,不仅降低了Viterbi译码器实现的复杂度,而且较好地均衡了面积和速度相互制约的矛盾。     

基于IP核的Viterbi译码器实现

Viterbi译码器在通信系统中应用非常普遍,针对采用DSP只能进行相对较低速率的Viterbi译码的问题,人们开始采用FPGA实现高速率Viterbi译码。本文首先简单描述了Viterbi译码的基本过程,接着根据Viterbi译码器IP核的特点,分别详细介绍了并行结构、混合结构和基于混合结构的增信删余3种Viterbi译码器IP核的主要性能和使用方法,并通过应用实例给出了译码器IP核的性能仿真。     

一种基于FPGA的Viterbi译码器的研究与设计

针对通信系统中传统维特比(Viterbi)译码器结构复杂、译码延时大、资源消耗大的问题,提出了一种新的基于FPGA的Viterbi译码器设计。结合(2,1,7)卷积编码器和Viterbi译码器的工作原理,设计出译码器的核心组成模块,具体采用3比特软判决译码,用曼哈顿距离计算分支度量,32个碟型加比选子单元并行运算,完成幸存路径和幸存信息的计算。幸存路径管理模块采用Viterbi截短译码算法,回溯操作分成写数据、回溯读和译码读,以改进的流水线进行并行译码操作,译码延时和储存空间分别降低至和。     

基于IP Core的Viterbi高速译码器测试

深入研究了基于Altera的Viterbi v4.3.0 IP核实现高速维特比译码器的测试方法,详细分析了译码器的Atlantic接口信号,给出了采用Paralle1结构Viterbi译码器的仿真结果.研究结果表明应用Viterbi v4.3.0能够设计出符合不同性能要求的高性能维特比译码器,采用面向数据包传输的Atlantic接口使Viterbi译码器具有很高的吞吐量.     

基于FPGA的卷积码Viterbi译码器性能研究

基于FPGA的卷积码Viterbi译码器,其性能与译码算法参数设置密切相关。在采用VHDL语言设计实现译码器的基础上,通过仿真,分析了Viterbi译码器参数的设置情况,就幸存路径长度、编码存储度等参数对FPGA译码器性能的影响进行了讨论,并给出了这些参数的最佳取值。对卷积码编译码参数设计具有较好的指导性和实用性。     

基于Xilinx FPGA的高速Viterbi回溯译码器

分析了新一代通信系统的发展对Viterbi译码器速率提出了更高的要求，通过优化Viterbi译码器结构，在Xilinx Virtex II PFGA上实现了速率30Mb／s以上的256状态Viterbi软译码。     

一种基于滑窗回溯多标准Viterbi译码器

为满足当前通信系统中存在的多种通信标准要求,提出了一种基于滑窗回溯的多标准Viterbi译码器。与其他Viterbi译码器相比,该译码器在支持任意长度序列译码的基础上,实现了1/2、1/3和1/4三种不同码率的配置,并适配5~9五种可变约束长度。此外,该译码器还具有软判决和硬判决两种判决模式,其中软判决采用8 bit有符号数量化。在对路径度量防溢出及幸存路径管理等模块进行优化后,该译码器能够在不显著增加延迟的前提下,具有更优异的工作性能。实验结果表明,该译码器可以根据设置的参数适用多种通信标准,并得到更好的误码性能。     

（2,1,7）卷积码编译码器的FPGA实现

卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且（2,1,7）卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出（2,1,7）卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快。阐述了编译码器各模块的设计原理,并在ModelSim给出各模块的仿真测试结果。同时对译码器进行纠错性能测试,测试结果表明该Viterbi译码器有良好的纠错性能。     

适用于 SBAS和 Galileo 卫星导航接收机的 Viterbi 译码器实现

设计并实现了一种适用于SBAS和Galileo卫星导航系统的（2,1,7）卷积码的Viterbi译码器．由于卫星导航系统中的数据率不高,采用串行结构实现 Viterbi译码器,并且多通道复用同一译码器,以节省电路面积．此外,采用改进的加比选单元并通过寄存器交换法对幸存路径进行管理,以进一步优化电路结构．为了减少RA M 的使用,利用同址更新技术将路径度量累加值和幸存路径存储至RAM ．译码电路通过FPGA验证,采用SMIC65 nm工艺库进行综合,该译码器逻辑电路的面积为4738μm2．     

一种M-FSK信号的能量度量Viterbi软译码算法性能分析

Viterbi译码算法广泛应用于无线数字通信系统,一般采用比特对数似然信息(LLR)作为译码器的输入。针对M-FSK信号,该文提出一种采用信号解调得到的M维能量信息,直接作为译码器分支度量值,并给出了相应的Viterbi译码算法。在加性高斯白噪声(AWGN)和瑞利(Rayleigh)衰落信道下对所提算法的BER性能进行了理论推导,得到了闭合表达式。通过仿真验证了理论推导的正确性,与常规Viterbi算法相比,所提算法避免了比特LLR和分支度量值的计算,降低了算法复杂度和减少了信息损失,提高了M-FSK信号软解调Viterbi译码算法的BER性能,是一种更适用于工程实现的M-FSK信号的Viterbi译码算法。     

一种高速Viterbi译码器的优化设计及Verilog实现

文章设计了一种高速Viterbi译码器，该设计基于卷积码编码及其Viterbi译码原理，完成了Viterhi译码的核心单元算法的优化，并采用Verilog语言编程实现了卷积码编码器和译码器。仿真和综合的结果表明本文设计的译码器速率达50Mbit／s，同时译码器的电路规模也通过算法得到了优化。     

Practical applications of coding

Coding applications have grown rapidly in the past several years with cost-effective performance demonstrated on several channels. Convolutional coding with soft-decision Viterbi decoding has emerged as a standard technique and is particularly well adapted to the commnnication satellite channel. Decoder implementations are discussed and examples are cited. Robustness of code performance is emphasized and instances of actual coding gain surpassing theoretical or basic coding gain are given. Some promising future directions are noted.     

Viterbi Decoder ACS单元中路径度量值存储空间的优化

ACS单元的设计及路径度量(PM)值的存储是Viterbi Decoder硬件实现的重要部分之一。介绍了一种码率为1/2的硬判决Viterbi Decoder的ACS部分的硬件实现方法。采用了一种全新的设计与存储方式,即原位运算旋转地址的方式,极大地节省了在ACS运算过程中用以存储路径度量值的RAM空间,大量的实验证明,设计的译码器在资源消耗上有较大优势。     

State diagram connectivity and its effects on the decoding ofshift-register-based codes

Coding performance is limited not only by Shannon's (1950) bounds but also by the complexity of decoders. Decoder complexity is in turn governed by the need for the different pieces of the machine to communicate with one another. This paper calculates lower limits on the intra-system information flow for the Viterbi decoding of shift-register-based codes, e.g., convolutional codes. These limits provide practical guidance for the construction of decoders for the current generation of convolutional and trellis codes. In particular, these bounds prove that a very specialized decoder family, called graph partition decoders, have an asymptotically optimum communications growth rate. The techniques used in this paper can, moreover, be applied to the design of new (non-shift-register-based) codes which may possibly circumvent the limits derived in the paper and to the design of parallel processors     

An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting

A new channel decoder LSI, which will be used in digital satellite TV broadcasting Set-Top Boxes, has been designed. This LSI's functions include AD/DA conversion, QPSK demodulating, Viterbi decoding, frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) decoding, and descrambling. We use a new method for Viterbi Decoding called the Tracking Survivor State Information (TSSI) method, which not only reduces power consumption, but also solves the problem of increasing memory size. To reduce the size of RS decoder circuit, we used a three-stage-pipeline structure as well as designed a new architecture to realize Euclid's algorithm. This device has been fabricated in a 0.35 µm 3-metal CMOS standard cell-based process and is composed of 670 K transistors. In this paper, we describe the TSSI method of the Viterbi Decoder and the Reed-Solomon Decoder's new 3-stage pipeline architecture.     

无线通信系统维特比译码的FPGA仿真验证

在设计宽带无线通信系统的基带平台中,采用一种基于FPGA仿真工具Active HDL和目前广泛用于数字信号处理、数值分析等的实用软件Matlab相结合的方法,通过实现(2,1,7)卷积编码的全并行维特比软判决译码的FPGA设计仿真和算法验证,提出一种利用Matlab进行测试向量的生成和验证,以简化仿真测试序列的手工输入,提高FPGA设计进程和保证代码质量的方法。     

Near-Minimum Bit-Error Rate Equalizer Adaptation for PRML Systems

Receivers for partial response maximum-likelihood systems typically use a linear equalizer followed by a Viterbi detector. The equalizer tries to confine the channel intersymbol interference to a short span in order to limit the implementation complexity of the Viterbi detector. Equalization is usually made adaptive in order to compensate for channel variations. Conventional adaptation techniques, e.g., LMS, are, in general, suboptimal in terms of bit-error rate (BER). In this paper, we present a new equalizer adaptation algorithm that seeks to minimize the BER at the Viterbi detector output. The algorithm extracts information from the sequenced amplitude margin (SAM) histogram and incorporates a selection mechanism that focuses adaptation on particular data and noise realizations. The selection mechanism is based on the reliability of the add compare select (ACS) operations in the Viterbi detector. From a complexity standpoint, the algorithm is essentially as simple as the conventional LMS algorithm. Moreover, we present a further simplified version of the algorithm that does not require any hardware multiplications. Simulation results, for an idealized optical storage channel, confirm a substantial performance improvement relative to existing adaptation algorithms.     

Good trellises for IC implementation of Viterbi decoders for linearblock codes

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of the IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VLSI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered     

Complexity reduction for a multisensor Viterbi equaliser

A multisensor equaliser based on the Viterbi algorithm is presented. The equaliser consists of a multisensor Viterbi estimator and adaptive channel estimators. Its complexity is described and its performance over mobile channels is analysed. It is concluded that the multisensor Viterbi equaliser is capable of considering truncated channels, thereby allowing a considerable reduction in complexity     

Implementation of microprocessors in trellis decoding of convolutional codes

The complexity of the digital circuit concerned with the trellis (Viterbi) decoder of a convolutional code is greater than other channel coding-decoding techniques, and it is recognised that the use of such a powerful coding-decoding technique in commercial data and voice communications systems is a serious problem. A prospective solution is to use a microprocessor system to combat the complexity of the system. A case study for implementing a common 8-bit microprocessor system is given; some results are presented and some space against speed trade-offs are discussed.