Fixed-gain CMOS differential amplifiers with no external feedback for a wide temperature range

We present original CMOS amplifiers designed for the DC to 10 MHz frequency range and operating in the 70-380 K temperature range. Aimed applications concern readout circuitry to be associated with THz bolometric pixels (either high-T_c superconducting or uncooled semiconducting), which require accuracy, low noise and low power consumption. Two designs are described that both exhibit high fixed-gain (40 dB) in a feedback-free architecture, which is based on a new low-transconductance composite transistor for an accurate control of this gain. Both amplifiers have been realized in a regular 0.35 μm CMOS process and tested in the 4.2-380 K temperature range, exhibiting good agreement between designed and measured characteristics.     

A Delay Generation Technique for Narrow Time Interval Measurement

A new architecture for the on-chip measurement of short-time intervals is proposed in this paper. The measurement method is similar to a typical low-voltage measurement setup where the input signals are first amplified and then measured to relax the dynamic range of the succeeding analog-to-digital converter. In the proposed method, narrow time intervals are first amplified by a time amplifier (TAMP) and then measured by a time-to-digital converter. A delay-locked-loop (DLL) circuit is utilized to design a feedback time amplifier in which the gain is readily programmed by input data to any integer value within a range specified by the number of delay cells in the DLL. The TAMP's gain remains rather unchanged under process and temperature variations due to the inherent negative feedback of the DLL system. The circuit is implemented using complementary metal--oxide semiconductor (CMOS) 0.18- $muhbox{m}$ technology occupying less than 0.63 $hbox{mm}^{2}$ of the silicon area. The simulation results show that the proposed scheme can successfully be employed to measure time intervals in the range of a few tens of picoseconds with acceptable accuracy.      

CMOS 图像传感器的发展现状

目的　了解当前 CMOS图像传感器的发展状况 .方法　详细介绍了图像传感器的历史背景、发展现状、像素单元的结构、工作原理以及 CMOS图像传感器芯片的整体结构 ,并比较了 CMOS图像传感器和 CCD图像传感器的优、缺点 .结果　指出了 CMOS图像传感器发展趋势 .结论　 CMOS图像传感器具有美好的发展前途     

COSMOS-a novel MOS device paradigm

Downscaling alone is not sufficient to sustain the development of CMOS devices, and further paradigm shifts are necessary. In this paper, we argue such a shift is possible and show through technology computer-aided design simulations that a symmetrically operating CMOS device pair may be built under a single gate structure by a surprisingly simple choice of device layout and channel engineering parameters. As a result, we predict that another seemingly fundamental CMOS architectural requirement, the need to build two separate MOSFETs with individual gate stacks, may be eliminated. We call this new architecture a complementary orthogonal stacked MOS (COSMOS), which places the n and p MOSFETs perpendicular to one another under a single gate, integrating them vertically, as well as laterally. We demonstrate how the device may be built, operated, and optimized for symmetric operation, as well as verifying logic NOT operation via three-dimensional device simulations. The COSMOS architecture would not only mean significant savings in the active device area of a conventional digital CMOS layout, but also reductions in RC device parasitics associated with building and wiring two sets of devices for a single Boolean output function.     

Design, Modeling, and Characterization of a Novel Circular Surface Acoustic Wave Device

The design, modeling, and fabrication of a novel circular surface acoustic wave (SAW) device in complementary metal oxide semiconductor (CMOS) are introduced. The results obtained in authors' previous work demonstrated that it is possible to design and fabricate SAW-based sensors in CMOS with comparable performances to conventional devices. It is of great interest to improve the transfer characteristics and to reduce the losses of conventional rectangular SAW architectures for obtaining highly selective sensor platforms. Performance deficiencies of regular SAW devices in CMOS were addressed with this new architecture for improved performance. A 3-D model for the novel architecture was constructed. A detailed finite-element analysis was carried out to examine the transient, harmonic, and modal behavior of the new architecture under excitation. The devices were fabricated in 0.5 $~mu$m AMI semiconductor technology and the postprocessing was carried out using cost-effective CMOS compatible methods. The results demonstrate that it is possible to obtain highly oriented SAWs by using the novel circular architecture. A 12.24 dB insertion loss improvement was achieved when compared with a conventional rectangular device that was fabricated in the same technology .      

Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array

A capacitor-free CMOS low dropout regulator (LDR) using the nested Miller compensation with an active resistor (NMCAR) is presented. It can efficiently control the damping factor and reduce the required Miller compensation capacitance. It can also resolve the trade-off between dc loop gain and damping factor, which existed in the LDR using the nested Miller compensation. To reduce the total Miller compensation capacitances further, a capacitor-free CMOS LDR using both the NMCAR and a 1-bit programmable capacitor array is presented. For this LDR, the total on-chip compensation capacitance is reduced 40% without influencing its stability. Furthermore, it also enhances the recovery time, compared with the LDR using the NMCAR technique. Two proposed LDRs with bandgap voltage references have been fabricated in a 0.35mum CMOS process. They can operate with and without output capacitors.     

Ink‐Jet Printed CMOS Electronics from Oxide Semiconductors

Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all‐oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution‐processed/printed transistors. As a major step toward solution‐processed all‐oxide electronics, here it is shown that using a highly efficient electrolyte‐gating approach one can obtain printed and low‐voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation.     

Thread‐Like CMOS Logic Circuits Enabled by Reel‐Processed Single‐Walled Carbon Nanotube Transistors via Selective Doping

The realization of large‐area electronics with full integration of 1D thread‐like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread‐like fiber electronic devices can be achieved using a simple reel‐to‐reel process, which is strongly required for low‐cost and scalable manufacturing technology. Here, high‐performance reel‐processed complementary metal‐oxide‐semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical‐doped single‐walled carbon nanotube (SWCNT) transistors. With the introduction of selective n‐type doping and a nonrelief photochemical patterning process, p‐ and n‐type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high‐performance and reliable thread‐like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel‐coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well‐aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p‐ and n‐type SWCNT transistors exhibit field‐effect mobility of 4.03 and 2.15 cm² V^?1 s^?1, respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V.     

与CMOS兼容的MEMS气压传感器工艺实现与性能分析

采用CMOS标准工艺,同时采用三种典型MEMS后处理关键工艺,重点通过对牺牲层释放工艺进行研究,制作实现了一种新型CMOS兼容的电容式气压传感器．在该传感器结构中,作为牺牲层的是在CMOS工艺中形成的掺硼氧化硅．通过释放使电容上电极悬空从而感应气压变化．释放过程采用氢氟酸HF、氯化铵、甘油和水的混合溶液．由于释放孔大小和释放孔间距的设计十分关键,通过实验验证优化了4μm×4μm的释放孔更适用于此传感器结构,并对此结构进行了性能分析与实验测试．结果表明,该气压传感器结构合理,工艺成功,重点解决了MEMS后处理中的牺牲层释放工艺与CMOS标准工艺的兼容问题,为利用CMOS标准工艺进行MEMS传感器的研制做出了有益的尝试．     

低频、低功耗CMOS LNA的设计优化技术

分析了具有源级退化电感的CMOS共源共栅结构电路在低频、低功耗LNA设计中存在的缺陷,为满足低频、低功耗设计的要求,现广泛采用在该电路结构基础上再并联栅极电容的结构.今按照噪声系数的定义严格推导了该结构电路的噪声参数表达式,并基于推导的公式分析了该结构在CMOS低频、低功耗LNA设计中的重要应用.最后实现了一个基于0.18μm CMOS工艺的ISM频段应用的433 MHz LNA的设计,运用Agilent公司的设计仿真软件ADS进行仿真,整个LNA的设计过程及ADS仿真结果与理论分析一致.     

Homogeneous 2D MoTe2 CMOS Inverters and p–n Junctions Formed by Laser‐Irradiation‐Induced p‐Type Doping

Among all typical transition‐metal dichalcogenides (TMDs), the bandgap of α‐MoTe₂ is smallest and is close to that of conventional 3D Si. The properties of α‐MoTe₂ make it a favorable candidate for future electronic devices. Even though there are a few reports regarding fabrication of complementary metal–oxide‐semiconductor (CMOS) inverters or p–n junction by controlling the charge‐carrier polarity of TMDs, the fabrication process is complicated. Here, a straightforward selective doping technique is demonstrated to fabricate a 2D p–n junction diode and CMOS inverter on a single α‐MoTe₂ nanoflake. The n‐doped channel of a single α‐MoTe₂ nanoflake is selectively converted to a p‐doped region via laser‐irradiation‐induced MoO_x doping. The homogeneous 2D MoTe₂ CMOS inverter has a high DC voltage gain of 28, desirable noise margin (NM_H = 0.52 V_DD, NM_L = 0.40 V_DD), and an AC gain of 4 at 10 kHz. The results show that the doping technique by laser scan can be potentially used for future larger‐scale MoTe₂ CMOS circuits.     

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.     

Polarization-switching D/A converter

This paper describes a novel digital-to-analog (D/A) conversion technique, which uses the analog quantity polarization as a D/A conversion medium. It can be implemented by CMOS capacitors or by ferroelectric capacitors, which exhibit strong nonlinearity in charge versus voltage behavior. Because a ferroelectric material inherently has spontaneous polarization and generally has a large dielectric constant, the effective capacitance of a ferroelectric capacitor is much larger than that of a CMOS capacitor of the same size. This ensures less influence of bottom-electrode parasitic capacitance on a ferroelectric capacitor. Furthermore, a data converter based on ferroelectric capacitors possesses the potential nonvolatile memory function owing to ferroelectric hysteresis. Along with the architecture proposed for polarization-switching digital-to-analog converter (PDAC), its circuit implementation is introduced. Described is implementation of two 9-bit bipolar PDACs: one is based on CMOS capacitors and the other on off-chip ferroelectric capacitors. Experimental results are presented for the performance of these two prototypes.     

Crystalline-silicon-based infra-red LEDs and routes to laser diodes

We review progress in silicon LEDs using dislocation engineering to achieve high temperature operation, a process that is fully CMOS (Complementary Metal Oxide Semiconductor) compatible. We concentrate on devices operating in the near infra-red where high value applications are. The need for silicon emitters, lasers and optical amplifiers is discussed followed by an outline of previous approaches and possible future routes explored. Results on gain in silicon are reported and routes to electrically pumped injection lasers and optical amplifiers considered. Extension of 1.1 and 1.5 μm devices to other wavelengths is discussed.     

Impact of line width roughness on the matching performances of next-generation devices

It is now widely accepted that line width roughness (LWR) reduces transistor performances and is a critical factor, along side gate leakage and short-channel effects, for device scaling at the 45 nm technology node and beyond. As new process modules and device architecture options are emerging, we report on a methodology that has been developed to study the impact of line width and LWR uncertainties at the device level. By investigating the matching performances of both planar CMOS and FinFETs, we evaluate the sensitivity to roughness of important electrical parameters like the off-current or the threshold voltage.     

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

A high fill-factor self-buffered active pixel sensor and a tunable injection current compensation architecture for high dynamic range imager are proposed for scaled standard CMOS technology. The new cell, including a photo diode formed by n-well and p-type substrate and an one-transistor output buffer, shows enhanced characteristics in output voltage swing and sensitivity compared with conventional APS. The imager can achieve fill-factor of 55%, sensitivity of 3.4 V/sec-lux, and large output swing of 2.2 V at V/sub DD/=3.3 V for 0.25-/spl mu/m CMOS technology. In addition, the proposed tunable injection current compensation architecture can improve dynamic range by as much as 40 dB and can be tailor designed to meet various application specifications. A dynamic range of up to 120 dB is projected by simulation results. Experimental results of the new structure, as well as simulated design of the circuit, are presented.     

Parasitic-aware robust concurrent dual-band matching network for a packaged LNA

A generalised form of a concurrent dual-band matching network has been proposed for a packaged CMOS low noise amplifier (LNA). To eliminate the detrimental effects of component non-idealities on matching performance, a modified set of design equations has been developed. The robustness of the proposed network has been demonstrated at the GSM900 and DCS1800 bands. Incorporating this network, an LNA designed in a 0.18 mum CMOS process provides S ₁₁ of -33 and -30-dB, gain of 16.54 and 11.03-dB and noise figure of 1.35 and 2.37-dB, respectively, at 900-MHz and 1.7-GHz. The LNA draws a current of 2-mA from 1.8-V supply.     

A New Spatiotemporal CMOS Imager With Analog Accumulation Capability for Nanosecond Low-Power Pulse Detections

High-speed cameras use the interesting performances of CMOS imagers that offer advantages in on-chip functionalities, system power reduction, cost, and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, a new imager called FAMOSI 2, which implements an electronic shutter and analog accumulation capabilities inside the pixel, is presented. With this kind of pixel and the new architecture for controlling the integration, FAMOSI 2 can work in repetitive mode for low light power and in single shot mode for higher light power. This repetitive mode utilizes an analog accumulation to improve the sensitivity of the system with a standard n-well/$ p_ sub$photodiode. The characterization has been realized in single shot mode to optimize the accumulation mode. The prototype has been fabricated in the Austriamicrosystems 0.35-$muhboxm$CMOS process. The chip is composed of 64 columns$times$64 rows of pixels. The pixels have a size of 20$muhboxm$$times$20$muhboxm$and a fill factor of 47%.     

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.     

SPICE macromodel and CMOS emulator for memristors

In this paper, a new SPICE macromodel and CMOS emulator for memristors are proposed and verified to fit to the memristor's model equation very well in the entire range of memristor's resistance from the RESET state to the SET state. Compared with the memristor's model equation, average percentage errors in the new SPICE macromodel and in the 4-bit CMOS emulator are less than 0.5% and 0.9%, respectively. In addition, the CMOS emulator for memristors which can be implemented by a CMOS circuit will be very useful to design and verify various peripheral circuits for memristor applications particularly when the memristor fabrication process is not ready.