A CdSe-CdTe thin-film transistor

Thin-film transistors were made on polycrystalline CdSe-CdTe semiconducting films prepared by flash evaporation of mixed CdSe and CdTe powders.     

Double-gate thin-film transistor

A thin-film transistor (t.f.t.) with opposing gate electrodes completely isolated from the source-drain circuit has demonstrated greater conductivity modulation with the signal applied between the two gates than the same t.f.t. connected with the signal applied between a gate and the source in the conventional manner. This result precludes the assumption that charge injected into the semiconductor region accounts for the modulation.     

Active-gate thin-film transistor

A thin-film transistor (TFT) with a lightly-doped offset built in the polysilicon gate is proposed. The offset region of the gate acts as a dielectric in the OFF state and as a conductor in the ON state. The unwelcome peak of the electric field near the drain in the OFF state is significantly reduced, as has been confirmed by two-dimensional device simulation. The key advantage of this device over conventional passive offset structures is that the ON current is not reduced, while the OFF current is suppressed by several orders of magnitude     

A new bottom-gated poly-Si thin-film transistor

We have proposed and fabricated the new bottom-gated poly-Si TFT with a partial amorphous-Si (a-Si) region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the reverse leakage currents are decreased significantly in the new poly-Si TFT compared with conventional one. This reduction is due to the suppression of field emission currents by local a-Si region like that of a-Si TFTs while the ON currents are kept almost the same due to the considerable inducement of electron carriers in the short a-Si channel by the positive gate bias     

A thin-film transistor for flat planel displays

This paper reports the measured results of a thin-film transistor (TFT) for the flat panel display application. The TFT has a double-gate structure and uses a very thin (80-100 Å) CdSe film as the semiconductor. The device has less than 10^-10-A zero-gate-bias leakage current and greater than 10⁶ON/OFF current ratio. It has been found that the only severe stability requirement on the device is in the OFF condition, Both dc and dynamic life tests have been made. The device performs better in the multiplexed condition than in the dc condition. Excellent maintenance of device parameters has been observed.     

A novel depletion-gate amorphous silicon thin-film transistor

A novel type of amorphous silicon (a-Si) thin-film transistor (TFT) in which a depletion gate is added to the top of the second nitride layer of a conventional a-Si TFT has been fabricated. In this transistor, switching is done by the depletion gate instead of the accumulation gate as in conventional a-Si TFTs. The pinch-off voltage and ON-OFF current ratio of the transistor can be changed by the accumulation gate bias. The transistor exhibits high ON-OFF current ratio, low contact resistance, and low gate-source capacitance     

A novel gate-overlapped LDD poly-Si thin-film transistor

We fabricate a new polycrystalline silicon thin-film transistor (poly-Si TFT), called a gate-overlapped lightly doped drain (GO-LDD) TFT, which reduces the leakage current without sacrificing the ON current. A new GO-LDD TFT, of which the electrical characteristics are tolerable to the change of LDD doping concentration, can be easily fabricated by employing the buffer oxide without any additional LDD implantation. The change of ON current due to the misalignment of the LDD region may be eliminated. Experimental results show that the leakage current of the proposed TFT's is reduced by two orders of magnitude, compared with that of conventional nonoffset TFT, while the ON current is not decreased. It is observed that the ON/OFF current ratio is not changed significantly with LDD doping concentration and LDD length     

An adaptive thin-film transistor

A thin-film transistor (TFT) is described whose transfer characteristic can be reversibly adapted by a short duration voltage pulse applied to a high impedance gate electrode. The device is a four-terminal two-gate structure. A source, drain, and insulator gate contact form the basic TFT, while the amount and polarity of the polarization charge on the surface of the ferroelectric material of a second gate contact determines the pinchoff voltage of the TFT transfer characteristic. Measurements on experimental units demonstrate that the pinchoff voltage is adjustable over a sizable range, and that TFT transconductance changes in excess of 1000 to 1 can be obtained. The time required to change between different states of the TFT characteristic is limited by the switching time of the ferroelectric material which, in general, can be of the order of microseconds. Electrical instabilities in the transfer characteristics of the devices, however, may limit their practical circuit application. The instabilities are observed as a slow time variation of pinchoff voltage after a state has been established. Experimental units use triglycine sulfate for the ferroelectric material and tellurium-silicon monoxide thin film transistors.     

Coplanar-electrode thin-film InSb transistor

A thin-film transistor, using very thin flash-evaporated and annealed InSb films as semiconductor in a coplanar-electrode structure, is characterized by a relatively large transconductance and a well-defined saturation region.     

A self-aligned offset polysilicon thin-film transistor usingphotoresist reflow

A simple fabrication method for a self-aligned offset structure, which uses photoresist reflow, is developed to reduce the leakage current of polysilicon thin-film transistors (poly-Si TFTs). The reflow of photoresist can be controlled by varying photoresist thickness and reflow temperature. It is found that the reflow length increases in proportion to the photoresist thickness, and increases with increasing reflow temperature at less than 200°C for the AZ5214A photoresist. Poly-Si TFTs are successfully demonstrated with offset lengths of 0.4 and 0.6 μm, which show apparent reduction of the leakage current     

A high-performance thin-film transistor with a vertical offsetstructure

In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (μc-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT). This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFTs with a much higher drivability. The fabrication process is simple, low temperature (⩽300°C), and low cost, with a potential for high reliability     

Analysis of double-gate thin-film transistor

An analysis is made of a double-gate thin-film transistor structure, and equations are derived for current flow for different input conditions on each gate. The use of two independent gates allows the possibility of simultaneously maintaining depletion and enhancement regions along the channel, and Poisson's equation is used to find the field and potential distribution along the channel. It is shown that by proper manipulation of the second gate, characteristic curves ranging from the normal TFT "pentode" curves to "triode" curves can be obtained from the same device. A comparison is given of experimental and theoretical results.     

Fast organic thin-film transistor circuits

We have fabricated organic thin-film transistors and integrated circuits using pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam sputtered silicon dioxide as the gate dielectric and a double-layer photoresist process to isolate devices. These transistors have carrier mobility near 0.5 cm²/V-s and on/off current ratio larger than 10⁷. Using a level-shifting design that allows circuits to operate over a wide range of threshold voltages, we have fabricated ring oscillators with propagation delay below 75 μs per stage, limited by the level-shifting circuitry. When driven directly, inverters without level shifting show submicrosecond rise and fall time constants     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

A novel thin-film transistor with self-aligned field induced drain

In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷     

Experimental realization of floating-gate-memory thin-film transistor

CdSe thin-film nonvolatile memory transistors have been made using the concept of a double-insulator structure with a thin floating gate inserted at the interface of the two insulators. The thin floating gate enhanced the charging and charge-retention behaviors of the memory transistors. On/off conductance ratio of greater than 1000 has been achieved. Writing speed on the order of microseconds is possible.     

Strain sensitivity of thin-film InSb transistor

A thin-film InSb transistor with well-defined saturation at room temperature exhibits useful strain sensitivities.     

A four-vacuum-cycle lift-off process for the polycrystalline CdSe thin-film transistor

A photolithographic process is described for the fabrication of the polycrystalline CdSe thin-film transistor (TFT). This process only uses four vacuum cycles and four lift-off masks, without the need of sputter cleaning to prevent contamination. The devices made have a stability similar to the ones made by the single-vacuum process.