Reliability characteristics of high-k dielectrics

In this paper, recent results of Weibull slopes, area scaling factors, and breakdown behaviors observed for both soft breakdown and hard breakdown are discussed. These results would help to shed light on the breakdown mechanism of HfO₂ gate dielectrics. The Weibull slope β of the hard breakdown for both the area dependence and the time-to-dielectric-breakdown distribution was found to be β=2, whereas that of the soft breakdown was about 1.4 (EOT=14 Å). We also integrated the time-to-breakdown characteristics of HfO₂ under unipolar AC voltage stress on MOS capacitors. The results show that longer lifetime of HfO₂ has been observed when compared to constant voltage stress. Higher frequency and lower duty cycle in the AC stress resulted in longer lifetime. As thickness decreases, the amount of lifetime enhancement decreases. The enhancement of unipolar t_BD is attributed to less charge trapping during the “on time”, t_on and charge detrapping during the off time, t_off. It is proposed that time (τ_in) for charge to be trapped in HfO₂ is longer than t_on of unipolar stress under high frequency. In addition to experimental results, possible solutions are discussed.     

Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies

A review of the channel hot carrier (CHC) mechanism and its effects on n-MOSFET devices of deep submicron CMOS bulk technologies is presented. Even with power supply reduction (V_supply ≈ 1.0 V) CHC effects still limit aggressive transistor scaling. In this work it is shown that the “Lucky Electron Model” picture is not adequate to describe carrier heating under quasi ballistic transport. A more general physical picture is proposed, in which the driving force of the hot carrier damage is the “carrier dominant energy” determined by the energy convolution of the effective interface states generation (ISG) cross section (S_IT(E)) and the electron energy distribution function (EEDF) at given bias stress conditions. Both the CHC LEM and the energy driven approximations are derived. The latter is shown to be more adequate to describe the CHC degradation with supply voltage reduction. This approach allows an experimental quantification of S_IT(E).     

Failure mechanisms of Schottky gate contact degradation and deep traps creation in AlGaAs/InGaAs PM-HEMTs submitted to accelerated life tests

In this work we analyze degradation phenomena observed inpseudomorphic AlGaAs/InGaAs HEMTs with Al/Ti gate metallization, which have been submitted to accelerated tests at high drain-source voltage V_Ds and high power dissipation P_D. After these tests, we observe permanent degradation effects, consisting in electron trapping in the gate-drain access region, with consequent decrease in the longitudinal electric field and “breakdown walkout”, and in thermally-activated interdiffusion of the AI/Ti gate with decrease in the gate Schottky barrier height and increase in drain saturation current I_D. Rather than causing a degradation of therf characteristics of the device, these phenomena induce an increase in the associatedrf gain at 12 GHz, the other rf characteristics being almost unchanged. Overall, the most relevant failure mode observed is an increase of low-frequency transconductance.     

Threshold voltage degradation in plasma-damaged CMOS transistors — Role of electron and hole traps related to charging damage

The paper presents results of study of threshold voltage (V_T) degradation in CMOS transistors damaged by high-field charging. Fowler-Nordheim stress induced V_T degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. “Direct” and “reverse” antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously.     

Oxide reliability: influence of interface roughness, structure layout, and depletion layer formation

The charge to breakdown Q_bd and the breakdown voltage V_bd distributions obtained on 7.5 and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms are discussed in terms of the GOX interface roughness and the depletion effects during the stress. The observed influence of the interface roughness on the GOX properties seems to be very sensitive to the gate polarity during the stress or the injection direction of electrons. Especially the roughness of the interface through which electrons are injected into the gate oxide influences the oxide reliability. The effect of the interface roughness turned out to depend strongly on the test acceleration level. A possibility of masking of the roughness (reduction of the “effective roughness”) of the GOX/Si interface as a result of strong depletion at higher accelerations is discussed.     

Flexible complementary inverter with low-temperature processable polymeric gate dielectric on a plastic substrate

We report low-temperature processability of poly(4-vinylphenol) based gate dielectric by investigating the effect of composition and processing temperature on the thermal, mechanical and electrical characteristics of the gate dielectric. We found that the processing temperature of the gate dielectric could be reduced up to 70 °C by optimizing the composition of the gate dielectric solution. Based on this finding, we have fabricated a flexible organic complementary inverter by integrating n- and p-type organic thin-film transistors (OTFTs) with the low-temperature processable gate dielectric on a plastic substrate. Pentacene and F16CuPc were used as p-type and n-type semiconductor, respectively. The inverter shows that the swing range of V_out is same as V_DD, which ensures “zero” static power consumption in digital circuits. The logic threshold of the inverter with G5 gate dielectric cured at 70 °C is 21.0 V and the maximum voltage gain (∂V_out/∂V_in) of 8.1 is obtained at V_in = 21.0 V. In addition, we have discussed in more detail the characteristics of the OTFTs and the complementary inverter with respect to the process condition of the gate dielectric.     

Refined electrical analysis of two charge states transition characteristic of “borderless” silicon nitride

In this paper we evaluate the electrical properties of silicon nitride so called “borderless nitride” deposited by PECVD process in the pre metal dielectric stack. Thus metal/silicon nitride/semiconductor structures have been analysed by an original electrical characterization based on C(V) and I(V) hysteresises. The objective is to understand how this material, initially introduced as etch stop layer and contaminant diffusion barrier, can impact active device performances. It appears that silicon nitride contains a huge defect quantity characterized in a non steady state and strongly influenced by maximum voltage applied. These charges can be balanced between either positive and negative states and are suspected to be K centers defects existing under two paramagnetic states K⁺ and K⁻. In addition, a RF power variation of SiH₄/NH₃ ratio, giving refractive indexes from 1.94 to 2.77, have shown that flatband voltage shift decreases with [Si]/[N] ratio whereas leakage current increases.     

An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation

A compact analytical model for MOSFET channel-length modulation (CLM) based on momentum and energy-conservation of Boltzmann transport equation as well as quasi-2D formulation is presented. It is consistent with the generalized drift–diffusion formulation including the nonlocal electron temperature, which can be interpreted as being an effective CLM or effective velocity overshoot. The model has a simple familiar form of the “pinch-off” model, with one fitting parameter for the length- and bias-dependent effective saturation field and effective Early voltage. The model can be easily characterized with one measured I_ds–V_ds data and has been verified with submicron technology data for the full range of gate lengths and bias conditions.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

Electrical characterization of thiols self-assembled layers on GaP (1 1 1) structures

The experimental studies on III–V semiconductor compounds surface passivation phenomena are mainly dedicated to solve some technological problems as those regarding the ways to keep the chemical stability of native oxides on surfaces. Self-assembled monolayers (SAMs) provide a simple way to produce relatively ordered structures at a molecular scale, which seems to be capable to protect the clean surface against the evolution of oxidation process. In this respect, thin films of SAMs of aliphatic thiol (dodencanthiol—CH₃(CH₂)₁₁SH) and aromatic thiol (4, 4′ tiobisbenzenthiol-S (C₆H₄SH)₂ have been deposited on the surface of GaP (1 1 1) samples. The electrical properties measurements of some structures based on GaP compound was performed. There were recorded current–voltage (I–V) characteristics for complex structures AuGeNi/R-SH/GaP and AuGeNi/Ar-SH/GaP in darkness and also exposed to a Xe lamp. In dark and in “reverse bias” way, the I–V characteristics present the feature of a Zenner diode for GaP/Ar-SH and a gradual increase of current for GaP/R-SH. In dark and “in forward bias” way, the current increases as for a normal diode for both GaP/Ar-SH and GaP/R-SH structures. The complex structures (e.g.: In/AuGeNi/R-SH/GaP/R-SH/AuGeNi/In) are less sensitive to light. The SEM analysis performed on a GaP/R-SH surface shows a continuous packed up layer while GaP/Ar-SH looks like an inhomogeneous deposition of layers with different thickness regions. The diodes’ ideality factors determined from I–V characteristics are unusually high (n2) as a possible result of inhomogeneous Schottky contacts or due to ageing effects, in the field of degradation.     

Structural properties of V2O5 thin films prepared by vacuum evaporation

Vanadium pentoxide (V₂O₅) films were deposited on glass substrates by vacuum evaporation technique at various deposition temperatures (T_s) viz., 300, 473, 573, 623 and 673 K. The structural and microstructural properties of the films are analyzed using XRD and Raman scattering measurements. X-ray characterization revealed the films deposited at T_s473 K are amorphous and the film deposited at T_s573 K are polycrystalline with orthorhombic symmetry. The corrected lattice constant values are determined from Nelson-Riely plots. The lattice constants “a” and “c” are found to decrease with increase in the deposition temperature, which may be attributed to the increase in non-stoichiometry. Change in the preferred orientation is observed for films deposited at substrate temperatures 623 K which is likely to be governed by the recrystallization process. Various structural parameters such as lattice constants, grain size, and microstrain and dislocation density are determined and the influence of deposition temperature on the structural parameters are discussed.     

Numerical analysis of a SWEAT structure with an improved one dimensional nonlinear model

An improved one dimensional (1 − D) nonlinear model of the thermal response of the Standard Wafer-level Electromigration Accelerated Test (SWEAT) structure is described. The major improvement in this model are accurate predictions of the critical current density j_o; according to older models j_o is inversely proportional to the “power” I²R/R(T_s), while our model shows a different (increasing) trend and is confirmed by measurements. The ratio of the maximum temperature increase to the average temperature increase (γ) for the investigated structure depends on the relative change of the resistance and normalized current , and can be calculated within 1% from basic material and structure parameters. The model includes the edge correction factor α depending on the geometry of the structure (W_n/t_i), material parameters and stress current I. Using the corrected values for the edge correction factor, the maximum temperature increase in the SWEAT test structure can be calculated within less than 5°C.     

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ _inv is controlled by the voltage differenceV _P – V_ch, whereV _ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV _P is defined as the particular value ofV _ch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV _P – V_S andV _P – V_D. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentI _D is derived and expressed as the difference between a forward componentI _F and a reverse componentI _R. Each of these is proportional to a function ofV _P – V_S, respectivelyV _P – V_D, through a specific currentI _S. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.     

The effects of duty cycle and voltage swing of gate pulse on the AC-stress-induced degradation of nMOSFETs with N2O gate oxides

AC-stress-induced degradation in metal-oxide--semiconductor field-effect transistor (MOSFET) with N₂O-grown and N₂O-nitrided gate oxides was investigated, with emphasis on the duty cycle and voltage swing of the gate pulse. It is demonstrated that N₂O-oxide devices show a weaker duty-cycle dependence than thermal-oxide devices, with N₂O-nitrided oxide superior to N₂O-grown oxide. More significantly, opposite frequency dependence of the V_T shift is found between gate-pulse swings of 0–l/2 V_D and 0–V_D. The reasons are likely due to charge trapping and neutral-trap creation in the gate oxide.     

Defect centroid,patial distribution,and areal density in process-induced radiation-damaged IGFETs with gate insulators grown at 1000 and 800° C

IGFET devices were fabricated with “dry” gate oxides grown at 1000 and 800° C in the thickness range 5–50 nm. They were then exposed in an electrically unbiased state to Al K_α x-ray (1.49 keV) radiation to simulate process-induced ionizing radiation exposure. Gate oxide defects were measured before and after irradiation using optically assisted electron injection. Following irradiation and injection, the measured voltage shifts indicate that radiation-induced “extrinsic” defects are localized near, but not exactly at, the Si/SiO₂ interface.ΔV _T is found to be linear int _ox for oxide thicknesses where the top electrode resides above the defect region, and quadratic int _ox for thicknesses where the top electrode encroaches upon the defect region. For very thin oxides,ΔV _T is observed to approach zero. Application of a defect distribution model based on this behavior reveals that the oxidation temperature does not influence the distribution of radiation-induced defects, but does influence their concentration; with the 800° C oxides always containing more defects than the 1000° C oxides. A gate oxide thickness regime of less than 5-6 nm is identified in which radiation-induced threshold voltage shifts are observed to approach zero.     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Development of “kink” in the output I–V characteristics of pseudomorphic hemt's after hot-electron accelerated testing

Large decreases in the drain current in the linear and low V_ds region followed by a “kink” in the output I_d-V_ds characteristics have been found after hot electron stress test in AlGaAs/InGaAs/GaAs power pseudomorphic HEMT's. Decrease in the transconductance measured in linear region, increase in the drain parasitic resistance and trasconductance frequency dispersion have also been observed and attributed to the generation of electron traps in the gate-to-drain access region.     

Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing

Electrical characterization of the hafnium oxide (HfO₂) gate dielectric films prepared by Hf sputtering in oxygen was conducted. By measuring the current–voltage (I–V) characteristics at temperature ranging from 300 to 500 K, several abnormalities in the I–V characteristics are recorded. For temperatures below 400 K, the current–voltage characteristics in high field region can be plotted with the Fowler–Nordheim law but a stronger temperature dependence was observed. Large flatband voltage shifts in the Al/HfO₂/Si capacitor were observed. The capacitance–voltage characteristics and flatband shifts are found to depend strongly on the post-deposition annealing temperature and duration. To study the reliability against high electric field, constant voltage stressing on the samples was conducted. We found that the trap energy levels are shallow and the oxide traps can be readily filled and detrapped at a low bias voltage.