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提出了很多结合技术使得指令调度与寄存器分配之间进行一些信息交互,在没有引入过多溢出代码的情况下提高了指令级并行度,从而提高了性能。按照算法的特征分类介绍了几种影响力较大的算法,同时作了简单的评价和效果比较,最后介绍了有关指令调度和寄存器分配结合的一些新方向。 相似文献
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Digital signal processors (DSPs) with very long instruction word (VLIW) data‐path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multibank register architectures are being adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. This paper addresses the issues of reducing the spill code for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register‐file architecture provides the opportunity to spill‐out register values onto different register banks. We present a conceptual framework based on the universal and the proxy interference graphs to model the live ranges of registers for spilling codes to different register banks. Heuristic algorithms are then developed on the basis of this concept. By heuristically estimating the register pressure for each register file, we treat different register banks as optional spilling locations in addition to traditional spilling to memory. Experiments were performed on the parallel architecture core VLIW DSP with distributed register files by incorporating our proposed optimization schemes into an Open64‐based compiler. The experimental results show that our approach can improve the performances on average for DSPStone and MiBench benchmarks with spilling cases by 7.1% and 21.6%, respectively, compared with the one always handling spill code in memory. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
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寄存器分配与指令调度是编译器优化过程中的两项重要任务．由于这两个阶段通常是独立完成的，寄存器分配往往会引入不必要的伪相关，从而影响指令调度的效率和结果，影响最终性能的提高．本文提出了寄存器队列模型，并在其基础上提出了一种结合实现寄存器分配和指令调度的算法，该算法能够在保证每条指令的执行时间最早的同时使用最少数目的寄存器．它的另外一个优点是具有线性的时间和空间复杂度，而且易于硬件实现． 相似文献
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This paper describes the management of register spills in a retargetable C compiler. Spills are rare, which means that testing is a bigger problem than performance. The trade-offs have been arranged so that the common case (no spills) generates respectable code quickly and the uncommon case (spills) is less efficient but as simple as possible. The technique has proven practical and is in production use on VAX, Motorola 68020, SPARC and MIPS machines. 相似文献
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This paper describes the design and implementation of a register allocator that performs the allocation over the Program Dependence Graph (PDG) representation of a routine. The PDG representation has been used successfully as the basis for various scalar optimizations, as well as for detecting and improving parallelization for vector machines, multiple processor machines, and architectures that exhibit instruction level parallelism. Variations of the PDG have also been used for debugging and integrating different versions of a program via program-slicing, and to enable translation of imperative programs for data-flow machines and demand-driven graph reducers. By basing register allocation on the PDG, the register allocation phase may be more easily integrated and intertwined with other optimization analyses and transformations. In addition, the advantages of a hierarchical approach to global register allocation can be attained without constructing an additional structure used solely for register allocation. © 1998 John Wiley & Sons, Ltd. 相似文献
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Yonghua Hu Xin Zhang Shuying Wang Wei Liang Kuan-Ching Li 《Concurrency and Computation》2023,35(19):e7519
Array-unit dual-usage register is a kind of register resource that can be read or written as a whole or individually. It is mainly configured in processors with SIMD processing units and provides register-level speed data transfer between the scalar and vector processing units. To improve the efficiency of algorithms by using an array-unit dual-usage register, we investigate in this article the problem of adapting register allocation to code containing array-unit dual-usage register names. We propose a corresponding global register allocation method by combining the allocation of regular registers with array-unit dual-usage register, ensuring that the names of array-unit dual-usage register can be used in the input code of register allocation. Moreover, we present the processing framework of this method and the specific algorithms of some related vital aspects and demonstrate the working principles of the algorithms by an example. Experimental studies were conducted on a platform based on the FT-M7002 DSP core, and showing that our register allocation method can effectively handle codes containing array-unit dual-usage register names and support relevant application algorithms to improve their data transfer scheme. For some typical algorithms with input matrix, substantial performance improvements of twofold or higher are achieved. 相似文献
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针对基础数学库中的寄存器分配特点,提出一种基于多级分层策略的寄存器分配策略。考虑各类寄存器的使用特点,采用多级分层模型,合理地使用寄存器资源,缓解基础数学中寄存器资源不足的情况,减少甚至避免寄存器分配过程中产生的溢出,达到提高数学库性能的目的。实验结果证明,该分配策略能够将数学库中的函数性能提高6%以上。 相似文献
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提出一种基于加权相容图的可测性寄存器分配模型,给出一个基于可测寄存器分配准则的相容图边的权值公式,并运用改进的加权团划分算法对加权相容图进行处理,从而实现了在寄存器分配过程中同时考虑4个可测性准则,达到提高设计可测性的目的.实验结果表明了算法在可测性方面的有效性. 相似文献
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This paper uses timed petri net to model and analyze the problem of instructionlevel loop scheduling with resource constraints,which has been proven to be an NP complete problem.First,we present a new timed Petri net model to integrate functional unit allocation,register allocation and spilling into a unified theoretical framework.Then we develop a state subgraph,called Register Allocation Solution Graph,which can effectively describe the major behavior of our new model.the main property of this state subgraph is that the number of all its nodes is polynomial.Finally we present and prove that the optimum loop schedules can be found with polynomial computation complexity,for almost all practical loop programs.Our work lightens a new idea of finding the optimum loop schedules. 相似文献
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从本质上来说,最小割集问题与最大流问题是同一个问题。由于后者的实用性更强,人们对它投入的关注与研究也更多,因而实际中是通过最大流问题来求最小割集问题。最大流-最小割集定理给出了一种用最大流算法求最小割集问题的方法,但在实际应用中,这种方法有时显得繁冗并有些迂回。文章首先介绍了最大流、最小割集的相关概念,然后从实际应用出发提出了一种用最大流求流图最小割集的新算法。随后证明了该算法的正确性,并举例说明了这种算法思想在其它方面的应用。 相似文献
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We consider the problem of finding a maximum subset of a given set of wires connecting two rows of terminals with fixed positions, such that no wires in the subset cross. We derive an algorithm that runs in O(p + (n ? p) ? g(p + 1)) time, where n is the number of wires given and p is the maximum number of noncrossing wires; in many practically relevant cases, e.g., when p is very high, it needs only linear time. We show how an extension of the algorithm solves the more general problem, where the positions of some terminals have some flexibility, within the same time bound. 相似文献
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梁勇强 《计算机工程与应用》2011,47(19):54-59
为了确保生成无向图割集的递归收缩算法的正确性和稳定性,对算法中种子顶点是支点的情形进行了分析,并采取了新的处理策略。分析了支点具有一个非可吸簇的情形,引进附加吸入的概念,修正了种子顶点的BFSO值取值规则,解决了现有算法可能遗漏割集的问题。针对支点没有非可吸簇的情形,给出了一个新的处理策略,解决了现有算法在某些特殊输入条件下效率不高的问题,在理论上分析了新处理策略的有效性,并做了相应的实验比较,理论分析和实验比较均表明：新的处理策略采用提高了递归收缩算法的稳定性。 相似文献
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提出使用网表示可分配寄存器对象,通过对网的活跃性数据流分析,构造网的冲突图。与变量冲突图相比,将基于变量的节点分裂成基于网的节点,将同一变量的冲突关系分摊到多个网上,虽增加冲突图节点数量,但降低节点度数,使得用更少颜色对冲突图着色,即可减少所需寄存器的数量,生成更加高效的可执行代码,使存器分配更为灵活。 相似文献
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讨论了节点和边都有容量限制的无向平面网络中的两点间的最小截问题.传统方法是把节点和边都有容量的网络中的最小截问题转化为只有边有容量的问题,但该方法用在平面网络时不能保持网络的平面性,因此网络的平面性不能得到利用.使用传统方法的计算时间为O(n2logn)(其中n为网络的节点数).给出了可以充分利用网络平面性的方法.对源和汇共面的s-t平面网络,把最小截问题转化为平面图上两点间的最短路径问题,从而可以得到O(n)时间的算法;对一般的平面网络,给出了新的将节点和边都有容量的问题转化为仅边有容量问题的方法,这种转化方法不破坏网络的平面性,从而可以利用平面网络中仅边有容量问题的计算方法,使原问题在O(nlogn)时间内获得解决. 相似文献
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投机是指令调度克服指令间控制依赖的一种重要手段.投机一方面可以提高指令级并行带来性能改善,另一方面,它也可能拉长变量活跃区间,增大寄存器压力,导致变量溢出,从而恶化性能.前人的寄存器压力敏感的指令调度的方法,往往当调度区域内活跃变量个数超过阈值时一味保守地调度.考虑到每调度一条指令的收益和代价是不同的,通过具体分析一次投机调度的性能收益和溢出代价来有选择地投机指令,而不是仅仅考虑活跃变量的数目.实验表明,该方法能有效提高程序性能,对SPEC2000的整数例子,比不考虑寄存器压力的投机调度平均性能提高1.44%. 相似文献
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1 IntroductionLet G = (V, E) be a connected, undirected graph with a weight function W on the set Eof edges to the set of reals. A spanning tree is a subgraph T = (V, ET), ET G E, of C suchthat T is a tree. The weight W(T) of a spanning tree T is the sum of the weights of its edges.A spanning tree with the smallest possible'weight is called a minimum spanning tree (MST)of G. Computing an MST of a given weighted graph is an important problem that arisesin many applications. For this … 相似文献