热管散热技术在半导体照明光源上的应用

无论是LED功率器件还是模组，增加光输出的瓶颈是散热问题。增加功率使热量积聚，造成结温升高，而结温升高会导致发光效率下降、发光波长移动、寿命降低。散热的最理想方案无疑是利用产生的热量作为能源，将热量转移出器件，而将热管技术应用到灯具式模组的散热中，正是这种措施，突破了Haitz定律，使单个封装LED器件的光通量输出更快地达到通用光源的要求。     

CAD技术在微电子工艺设计及器件特性分析中的应用

集成电路工艺及器件特性计算机辅助设计系统是微电子ＣＡＤ系统的重要组成部分。本文介绍了该系统在集成电路工艺设计及器件设计中的部分应用。     

CAD技术在微电子工艺设计及器件特性分析中的应用

集成电路工艺及器件特性计算机辅助设计系统是微电子ＣＡＤ系统的重要组成部分。本文介绍了该系统在集成电路工艺设计及器件设计中的部分应用。     

宽禁带半导体功率器件在现代雷达中的应用

现代战争对雷达性能的要求日益提高,基础材料、工艺和元器件的飞速发展,促进了雷达技术的不断进步.宽禁带半导体功率器件的出现,使得雷达发射机乃至雷达性能的大幅度提升成为可能.文中简要介绍了现代雷达对大功率发射机的迫切需求,结合宽禁带半导体器件的特点,阐述了该类器件的发展现状,给出了发展趋势及应用展望.     

功率集成器件及其在通信中的应用

本文综述新一代电力半导体器件中、VDMOS、IGBT、高压集成电路、Smart功率集成电路及其最近发展动态以及上述器件在通信中的应用。     

纳米级应变硅MOSFET的有限元与TCAD模拟研究

基于有限元方法对一款具有SiGe源/漏结构的纳米PMOSEFT进行了建模与分析,沟道应变的计算结果与CBED实验测量值呈现良好的一致性,最小误差仅为1.02×10-4.对新型的SiC源/漏结构的纳米NMOSFET的类似研究表明,栅长越短,应变对沟道的影响越显著.另一方面,采用TCAD工具Sentaurus通过工艺级仿真...     

SACP技术在红外器件研制工艺中的应用探讨

各类半导体器件的性能几乎都与界面状态有关,研制高性能的红外探测元件首要的就是如何获得表面无污染、无损伤、结构完整的优质晶片。诚然,晶体结构的完整性取决於晶体生长,而晶片表面的污染,损伤则与晶片制作的各种工艺密切相关。本文介绍利用电子通道技术来检验半导体晶片表面的污染、损伤及结构完整性我们所进行的一些初步工作。对由同一晶锭上切割下的碲镉汞晶片任取10片分为两组进行了对比分析。结果表明在机械磨、拋     

浅谈SILVACO TCAD在VDMOS功率器件设计中的应用

SILVACO TCAD是一款半导体工艺和器件仿真的专用软件,具有良好的界面,精确的模型设计被广泛应用。本文利用SILVACO TCAD软件对VDMOS功率器件的工艺和器件参数进行仿真,根据仿真过程及结果,提出了该仿真软件应用过程应该注意的一些问题。     

RAID4技术及其应用

介绍一产现数据容错的方法，即对目前服务器中采用的“磁盘阵列”，通过数据冗余提高数据安全性从而达到对数据进行保护的方法。同时介绍了RAID的优点、分级及应用。     

功率MOSFET在开关电源中的应用

开关电源具有小型、高效、轻量等特点,广泛应用于工业类和消费类产品中,表1给出了其应用领域。 表1 开关电源应用领域     

基于TCAD软件的单层多晶EEPROM器件模拟分析

利用TCAD软件对单层多晶EEPROM器件特性进行了模拟分析,介绍了单层多晶EEPROM存储单元结构与原理的基础,针对TCAD软件中模拟分析单层多晶EEPROM器件特性时存在的困难,提出了一种两个MOS管外加电阻的等效模型来替代单层多晶EEPROM存储单元结构进行等效模拟.通过编程模拟了单层多晶EEPROM器件性能,模拟分析得到的特性曲线与理论曲线能较好吻合,验证了等效模型方案的可行性.     

On the assessment of various implants using 3D TCAD for FinFETs

This work deals with the junction and channel optimization on FinFET devices. The main objective was to show feasibility of a three-dimensional (3D) process simulation within the context of optimization of the device design and the underlying fabrication processes. The 3D simulation process flow is based on the development of the SOI based FinFET devices at Infineon. Similar to real devices, important 3D geometrical features, such as corner roundings and 3D facets have been introduced into the simulation setup, which is based on commercially available 3D process simulation software (Taurus 3D). The influence of various unit process steps, such as channel implant, and LDD implant on the electrical performance of the devices have been evaluated. Beside the successful demonstration of a functional 3D process simulation flow, detailed issues of process and device simulation methodology such as the usage of different dopant diffusion and mobility models are assessed. Finally, a comparison of the simulation results with electrical measurement data is performed which fairly shows excellent agreement.     

Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.     

一种新型的圆柱体全包围栅结型场效应管体管： 器件物理, 器件仿真, 器件工艺

We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.     

A novel GAAC FinFET transistor: device analysis, 3D TCAD simulation, and fabrication

We report the analysis and TCAD results of a gate-all-around cylindrical (GAAC) FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-l0 nm sizes.     

半导体器件/电路混合模拟及其在HPM效应中的应用

建立了自行研制的通用二维半导体器件数值模拟软件GSRES与电子电路仿真软件SPICE的接口;实现了半导体器件/电路混合模拟功能,从而将电子系统的高功率微波效应模拟容纳到电路模拟的框架下;给出对CMOS反相器及典型数字电路的混合模拟算例.计算结果验证了该方法的可行性及有效性.     

基于TCAD模拟的buffer单粒子效应解析分析

半导体器件和集成电路的辐射效应,其本质就是电子空穴对的产生和复合、电荷的传输与收集、界面态和氧化层陷阱电荷积累等一系列的物理过程。这些物理过程会受到各种因素的影响,例如上拉补偿管的尺寸、重离子入射角度、器件的外延层浓度等。本文使用TCAD器件/电路混合模式仿真了这些关键变量对buffer电路单粒子效应的影响。     

抑制亚微米NMOS穿通效应的Taurus WorkBench--TCAD优化

Taurus WorkBench是用于超深亚微米层次下的TCAD一体化仿真优化平台.在介绍了TWB的主要功能及实施要点之后,以亚微米NMOSFET器件的阈值电压及源漏穿通电压为响应变量,采用DOE方法进行仿真,并以仿真结果阐述了注入剂量及注入能量对阈值电压`和源漏穿通电压Vbrk的影响.     

基于TCAD的SRAM单粒子效应研究

针对40 nm体硅工艺利用TCAD(Technology Computer Aided Design)对关键NMOS进行3D建模,采用混合仿真模型对SRAM单粒子效应进行模拟仿真.通过改变重离子LET(Linear Energy Transfer)值、入射位置和入射角度,分析了其对单粒子效应的影响.实验结果表明40 nm工艺下单粒子效应各参数的变化与传统工艺一致.最后,基于R-C简化混合仿真模型,相比于混合仿真模型其电压、电流等参数具有较好一致性,验证了该模型对SRAM单粒子效应模拟的有效性.     

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (V_TH=0.59 V, S=90 mV/dec) and simulations (V_TH=0.50 V, S=92 mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO₂ interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.