Design of ternary adiabatic multiplier on switch-level

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be obtained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ternary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are characterized with distinctive low power consumption.     

Reversible energy recovery logic circuit without non-adiabaticenergy loss

The authors propose a reversible energy recovery logic (RERL) circuit for ultra-low-energy consumption, which consumes only adiabatic energy loss and leakage current loss by completely eliminating non-adiabatic energy loss. It is a dual-rail adiabatic circuit using the concept of reversible logic with a new eight-phase clocking scheme. Simulation results show that at low-speed operation, the RERL consumes much less energy than the complementary static CMOS circuit and other adiabatic logic circuits     

Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems.     

基于RT器件的三值与非门、或非门电路设计

共振隧穿（resonant tunnel,RT）器件本身所具有的微分负阻（negative differential resistance,NDR）特性使其成为天然的多值器件，文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性，该设计思想可推广到更高值的多值电路设计中。     

基于RT器件的三值与非门、或非门电路设计

共振隧穿(resonant tunnel,RT)器件本身所具有的微分负阻(negative differential resistance,NDR)特性使其成为天然的多值器件.文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性.该设计思想可推广到更高值的多值电路设计中.     

三值钟控绝热静态随机存储器设计

通过对多值逻辑、绝热电路和三值SRAM结构的研究,提出一种新颖的三值钟控绝热静态随机存储器(SRAM)的设计方案。该方案利用NMOS管的自举效应,以绝热方式对SRAM的行列地址译码器、存储单元、敏感放大器等进行充放电,有效恢复储存在字线、位线、行列地址译码器等大开关电容上的电荷,实现三值信号的读出写入和能量回收。PSPICE模拟结果表明,所设计的三值钟控绝热SRAM具有正确的逻辑功能和低功耗特性,在相同的参数和输入信号情况下,与三值常规SRAM相比,节约功耗达68%。     

nMOS reversible energy recovery logic for ultra-low-energyapplications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-μm CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V_dd=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V_dd=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.     

基于电路三要素理论的三值绝热加法器设计

通过对加法器和绝热电路工作原理及结构的研究,本文提出一种三值绝热加法器设计方案.该方案首先以电路三要素理论为指导,推导出一位三值绝热全加器的元件级函数式,并利用自举的NMOS管实现相应的电路结构,完成对电路的能量注入和恢复.然后在此基础上,进一步得到四位三值绝热加法器.最后 PSPICE模拟验证所设计的电路具有正确的逻...     

Design of ternary clocked adiabatic static random access memory

Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory (SRAM),a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.     

采用三相交流电源的低功耗绝热时序电路

研究采用三相交流电源的绝热时序电路.首先介绍了采用三相交流电源的双传输门绝热电路并分析其工作原理，在此基础上提出了性能良好的低功耗绝热D、T与JK触发器.使用绝热触发器设计时序系统的实例被演示.SPICE程序模拟表明，设计的电路具有正确的逻辑功能及低功耗的优点。     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

能量回收电路的功耗优化方法

能量回收电路的非绝热损失正比于CLΔV2,文中提出了两种方法降低CL和ΔV因子.HEERL(high efficient energy recovery logic)电路利用自举效应减小了回收节点的残留电压ΔV,IERL(improved energy recovery logic)电路增加了回收的通路,在控制回收通路的小电容节点产生了CAΔV2的非绝热损失,从而使大电容输出节点电荷被充分回收,降低了电路的整体功耗.降低非绝热损失两个因子CL和ΔV的能量回收电路与其它能量回收电路相比,电路面积增加很小(2个NMOS管),而功耗可降低50%以上.     

A 32×32-b adiabatic register file with supply clock generator

A 32×32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 μm complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit     

Digital circuit applications of resonant tunneling devices

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

一种新型的绝热低功耗逻辑电路

文中作者提出了一种新型的自举式 Adiabatic逻辑电路—— Pass Transistor-Bootstrap Charge Recov-ery logic(PT-BCRL) ,该电路的操作分为两级 ,第一级负责逻辑值的运算 ,采用传统的 ECRL电路 ,第二级电路通过利用自举效应经 NMOS管对负载进行充放电 ,使得其充放电为一全绝热过程 ;另外 ,第一级电路通过一互补传输门与第二级电路相连 ,使得该电路的能量的传输和恢复效率都显著得到提高。由于电路分两级操作 ,它很好地解决了传统 Adiabatic电路的功耗和负载电容值直接相关的问题 ,这在用 0 .6μm CMOS工艺器件参数进行的电路模拟中得到了初步验证     

基于连续逻辑的十值十进制算术运算电路的设计

本文提出了用ＤＹＬ系列器件构成的直接用十进制进行运算的十值电路。ＤＹＬ器件是一种线性元件,它可以工作于０－３Ｖ范围内的任意信号电压,对信号的分辨率极高,为实现高信息密度的十值电路提供了方便条件。本文提出的电路其工作原理是基于一种我们称之为“赋值－选通”的方法,将可能的输出值全部赋予电路,根据输入信息,通过选通电路直接将计算结果输出,这种赋值－选通法对多值电路的设计有普遍意义。     

An efficient charge recovery logic circuit

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V