基于交叉耦合结构的抗工艺偏差温度传感器

An innovative, thermally-insensitive phenomenon of cascaded cross-coupled structures is found. And a novel CMOS temperature sensor based on a cross-coupled structure is proposed. This sensor consists of two different ring oscillators. The first ring oscillator generates pulses that have a period, changing linearly with temperature. Instead of using the system clock like in traditional sensors, the second oscillator utilizes a cascaded cross-coupled structure to generate temperature independent pulses to capture the result from the first oscillator. Due to the compensation between the two ring oscillators, errors caused by supply voltage variations and systematic process variations are reduced. The layout design of the sensor is based on the TSMC13G process standard cell library. Only three inverters are modified for proper channel width tuning without any other custom design. This allows for an easy integration of the sensor into cell-based chips. Post-layout simulations results show that an error lower than ±1.1 °C can be achieved in the full temperature range from 40 to 120 °C. As shown by SPICE simulations, the thermal insensitivity of the cross-coupled inverters can be realized for various TSMC technologies： 0.25 μm, 0.18 μm, 0.13 μm, and 65 nm.     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena

In this paper, reliability of CMOS differential cross-coupled LC oscillators is examined, and a novel on chip aging detection and healing technique is developed to increase the lifetime of oscillator circuits. Aging causes degradation in several transistor parameters, such as threshold voltage, mobility, and transconductance. While these changes cause irregular timing characteristics and increased power consumption in digital circuits, the case is quite different for their analog counterparts. Analog circuits, especially nonlinear ones, show more deviations at the output due to parameter changes. In order to evaluate the aging effects on nonlinear analog circuits, two different oscillator structures (n-type and p-type) with 5 GHz oscillation frequency were designed using 0.13 μm technology. The phase noise analysis of fresh and aged oscillators was performed analytically and through simulations. Based on these analyses the robustness of oscillators was discussed. Finally, an on chip aging sensor and self recovery mechanism are proposed to increase the robustness of the CMOS LC oscillators.     

9.3-10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance

A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18-/spl mu/m CMOS technology. The complementary cross-coupled differential topology is adopted in the design. The measured phase-noise is around -89 dBc/Hz at the offset frequency of 100 kHz from the center frequency of 9.83 GHz, the output frequency tuning range of the fabricated VCO is 1.1 GHz ranging from 9.3 to 10.4 GHz, and the power consumption of the core VCO circuit is 5.8 mW. The design is the first one that adopts the complementary cross-coupled circuit structure for 10-GHz-band oscillators, and whose performances of the VCO are the best ones for 10-GHz-band oscillators, compared with the 10-GHz-band CMOS oscillators reported earlier.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

用于以太网物理层时钟同步PLL的VCO设计

研究了一种基于以太网物理层时钟同步的高带宽低噪声压控振荡器（VCO）,该VCO采用交叉耦合的电流饥饿型环形振荡器,通过级联11级环路电路和改善其控制电压变换电路,优化了VCO的输出频率范围以及降低了输出时钟的相位噪声,完全满足以太网物理层芯片时钟电路的性能指标。基于TSMC3．3V0．25μmCMOS工艺的仿真结果表明,中心频率为250MHz时,压控增益为300MHz／V,其线性区覆盖范围是60～480MHz,在偏离中心频率600kHz处的相位噪声为-108dBc。     

一种用于RFID标签带温度补偿的振荡器设计

提出了基于TSMC 0.18μm RF CMOS工艺带温度补偿高精度振荡器的设计方案。针对射频电子标签应用的设计要求,选用改进型的双电容张弛振荡器结构。通过温度补偿作用,参考电压与输出电流受电源影响较小,保证了振荡器输出频率的稳定性。使用SPECTRE工具对电路进行仿真,在1.8 V电源电压下,-25¹00℃范围内,中心频率为1.92 MHz时最大偏差小于±0.75%,达到使用的要求,并在此基础上完成电路的版图。     

A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider

Numerous circuit topologies have been proposed for divide-by-ρ injection-locked frequency dividers (ILFDs), most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. In this paper we present simulations of an RF CMOS ILFD that can operate equally well in both divide-by-2 and divide-by-3 modes. The ILFD is based on a cross-coupled CMOS LC oscillator with direct injection and an auxiliary injection path. The paper presents two variants of the circuit architecture and Cadence simulations in the multi-GHz frequency range using a standard TSMC 65 nm CMOS process design kit.     

A power-efficient wide-range phase-locked loop

This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-μm CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations     

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization

CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.     

Nonlinear analysis of a cross-coupled quadrature harmonic oscillator

The dynamic equations governing the cross-coupled quadrature harmonic oscillator are derived assuming quasi-sinusoidal operation. This allows for an investigation of the previously reported tradeoff between close-to-carrier phase noise and quadrature precision. The results explain how nonlinearity in the coupling transconductances, in conjunction with a finite amplitude relaxation time and de-tuning of the individual oscillators, cause close-to-carrier AM-to-PM noise conversion. A discussion is presented of how the theoretic results translate into design rules for quadrature oscillator ICs. SPECTRE RF simulations verify the developed theory.     

基于游标效应的高灵敏光纤温度和应变传感器

提出一种基于光纤Sagnac干涉仪(FSI)和偏振模干涉仪(PMI)级联结构的高灵敏光纤温度和应变传感器。FSI作为参考干涉仪,是将对温度、应变、弯曲及扭转不敏感的椭圆芯保偏光纤(ECPMF)引入到Sagnac环内制得的。PMI作为传感干涉仪,是对光纤起偏器与末端端面镀金的熊猫型保偏光纤(PMF)的快轴/慢轴以45°角进行熔接制得的。参考干涉仪的自由光谱区(FSR)易被调整为接近传感干涉仪的FSR,从而产生光学游标效应,实现灵敏度放大。实验结果表明:所设计的级联传感器的温度灵敏度达15.56 nm/℃,是单个PMI的11.12倍;应变灵敏度达154.04 pm/με,是单个PMI的11.81倍。所设计的传感器具有灵敏度高、制作简单、稳定性好等优点,在航空航天、工业生产等领域中具有广阔的应用前景。     

Linearity of bulk-controlled inverter ring VCO in weak and strong inversion

In this paper linearity of frequency modulation in voltage controlled inverter ring oscillators for non feedback sigma delta converter applications is studied. The linearity is studied through theoretical models of the oscillator operating at supply voltages above and below the threshold voltage of a transistor, bringing the transistors in respectively strong and weak inversion. The theoretical results are tested with more advanced models through spectreRF simulations. A soft rail approach implemented to improve linearity in weak inversion is proposed and demonstrated. The influence from voltage noise, process variations and temperature variations have also been simulated to indicate the advantages of having the soft rail bias transistor in the VCO.     

Cobalt oxide nanosheet humidity sensor integrated with circuit on chip

The work studies a micro humidity sensor integrated with a seven-stage ring oscillator circuit-on-a-chip fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The structure of the humidity sensor consists of interdigitated electrodes and a sensing film. The sensing film is cobalt oxide nanosheet that is prepared by a precipitation-oxidation method. The sensor, which is a capacitive type, changes in capacitance when the sensing film adsorbs or desorbs water vapor. The ring oscillator circuit is employed to convert the capacitance of the sensor into the oscillation frequency output. The post-process of the sensor includes etching the sacrificial oxide layer and coating the sensing film on the interdigitated electrodes.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点.从LC振荡器的模型出发,研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响.给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

A source degenerated LC quadrature VCO (SD-QVCO) using 0.18-μm SiGe BiCMOS

This letter presents a fully integrated BiCMOS quadrature voltage-controlled oscillator (QVCO). The QVCO consists of two nMOSFET cross-coupled oscillator stacked in series with source degenerated HBT transistors. SiGe HBT introduces low flicker noise compared to CMOS devices. To generate quadrature phase signals with strong coupling strength, the proposed design uses two MOS-coupled LC-tank cores instead of passive device-coupled cores. This source degeneration topology can improve the phase noise performance of the QVCO as compared to the sub-VCO. The proposed QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, can generate quadrature signals in the frequency range of 4.52–5.05 GHz with core power consumption of 5.76 mW at the dc bias of 1.8 V. At 4.53 GHz, phase noise at 1 MHz offset is ?124.52 dBc/Hz. The die area of the fabricated prototype is 0.453 × 0.898 mm².     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点. 从LC振荡器的模型出发，研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响. 给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

Multiscroll Chaotic Oscillators: The Nonautonomous Approach

A novel technique for designing chaotic oscillators capable of producing multiscrolls is presented. The technique is based on multilevel-logic pulse-excitation. A modified forced Van der Pol oscillator, a forced active tank resonator, and a forced cross-coupled oscillator are given as design examples.     

无线局域网接收机用频率综合器的关键技术

对无线局域网接收机用锁相环型频率综合器的几项关键技术进行了研究.首先分析了锁相环型频率综合器的结构并提出了系统的主要参数.采用TSMC 0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.其在4.189GHz频点上4MHz频偏处所测得的相位噪声为-117dBc/Hz.采用TSMC 0.18μm混合信号CMOS工艺实现了具有低功耗的下变频模块电路.该电路在1.8V电源供电下可正常工作,功耗为13mW.     

Divide-by-2 injection-locked frequency divider implemented with two shunt 4th-order LC resonators

A triple-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown that the ILFD has three locking ranges at fixed bias condition or by varactor bias switching.