Design of a 24–40 GHz balanced low noise amplifier using Lange couplers

A wide band （24–40 GHz） fully integrated balanced low noise amplifier （LNA） using Lange couplers was designed and fabricated with a 0.15 μm pseudomorphic HEMT （pHEMT） technology. A new method to design a low-loss and high-coupling Lange coupler for wide band application in microwave frequency was also presented. This Lange coupler has a minimum loss of 0.09 dB and a maximum loss of 0.2 dB over the bandwidth from 20 to 45 GHz. The measured results show that the realized four-stage balanced LNA using this Lange coupler exhibites a noise figure （NF） of less than 2.7 dB and the maximum gain of 30 dB; moreover, a noticeably improved reflection performance is achieved. The input VSWR and the output VSWR are respectively less than 1.45 and 1.35 dB across the 24–40 GHz frequency range.     

气象探空雷达中平衡式低噪声放大器设计

为了提高L波段气象探空雷达中射频前端的稳定性,采用ATF54143晶体管设计了一种平衡式结构的低噪声放大器。通过使用ADS软件对该低噪声放大器进行了优化、仿真,并进行了实物加工。实物测试表明,该低噪声放大器带内增益大于15dB,噪声系数小于1dB,稳定性系数大于1。     

60GHz平衡式单片低噪声放大器

与单端结构相比平衡式放大器具有更好的输入、输出回波损耗,更低的噪声系数,同时1dB压缩点提高3dB,IM3提高6dB,动态范围增加一倍。本文中,每一个单端放大器采用四级级联的方式以在宽频带范围内获得高增益。在59~64GHz范围内,平衡式放大器的小信号增益＞20dB;输入、输出回波损耗均＜-12dB;60GHz处,输出1dB压缩点达到10.5dBm;噪声系数的仿真结果＜3.9dB。芯片采用0.15μm GaAs pHEMT实现,面积为2.25mm×1.7mm。     

8～18 GHz微波低噪声放大器的设计与实现

采用平衡式结构设计了微波宽带低噪声放大器,测试结果:在频率为8～18GHz的宽带内增益大于30dB,增益平坦度小于3dB,噪声系数小于2.0dB,输入输出驻波比小于2.5,1dB压缩点输出功率为15.8dBm。该放大器制作在氧化铝陶瓷基板上。     

Design of on-chip 15-18 GHz ultra low noise amplifier

With rapid development communication system, high signal to noise ratio （SNR） system is required. In high frequency bandwidth, high loss, low Q inductors and high noise figure is a significant challenge with on-chip monolithic microwave integrated circuits （MMICs）. To overcome this problem, high Q, low loss transmission line characteristics was analyzed. Compared with the same inductor value of the lumped component and the transmission line, it has a higher Q value and lower loss performance in high frequency, and a 2-stage common-source low noise amplifier （LNA） was presented, which employs source inductor feedback technology and high Q low loss transmission line matching network technique with over 17.6 dB small signal gain and 1.1 dB noise figure in 15 GHz-18 GHz. The LNA was fabricated by WIN semiconductors company 0.15 μm gallium arsenide （GaAs） P high electron mobility transistor （P-HEMT） process. The total Current is 15 mA, while the DC power consumption is only 45 mW.     

一个8~18GHz的宽带高功率放大器

设计研制了一个8~18GHz的混合集成电路宽带高功率放大器。高功率放大器由基于GaAs MMIC工艺的4指微带兰格耦合器实现。为了减小电磁干扰,采用散热效果好的多层AlN材料作为功率放大器的载体。当输入功率为25dBm时,功率放大器输出连续波饱和功率在8–13 GHz 频率范围内大于39dBm,在其他频率范围内大于38.6dBm,在11.9GHz我们得到最大输出功率39.4dBm。在整个频带内,功率附加效率大于18%,当输入功率为18dBm时小信号增益为15.70.7 dB。高功率功率放大器尺寸为25mm*15mm*1.5mm.     

An 8-18 GHz broadband high power amplifier

An 8-18 GHz broadband high power amplifier(HPA) with a hybrid integrated circuit(HIC) is designed and fabricated.This HPA is achieved with the use of a 4-fingered micro-strip Lange coupler in a GaAs MMIC process.In order to decrease electromagnetic interference,a multilayer AlN material with good heat dissipation is adopted as the carrier of the power amplifier.When the input power is 25 dBm,the saturated power of the continuous wave(CW) outputted by the power amplifier is more than 39 dBm within the frequency range of 8-13 GHz,while it is more than 38.6 dBm within other frequency ranges.We obtain the peak power output,39.4 dBm,at the frequency of 11.9 GHz.In the whole frequency band,the power-added efficiency is more than 18%.When the input power is 18 dBm,the small signal gain is 15.7±0.7 dB.The dimensions of the HPA are 25×15×1.5 mm~3.     

Ku频段小型化低噪声放大器的设计

设计制作了一款基于微组装工艺的小型化低噪声放大器（LNA）。该器件广泛选用裸管芯、芯片电容等微型器件,采用两级放大电路结构,使用AWR与HFSS电磁仿真软件进行设计、优化和仿真,运用键合金丝微波特性进行噪声系数调试,实现较好的低噪声微波特性。最终实现了在12.25GHz-12.75GHz 工作频段,增益大于20dB,噪声系数小于1.2dB的低噪声放大器,整体电路尺寸仅为12mm×10mm×7mm。     

毫米波宽带高中频单平衡混频器设计与实现

针对毫米波宽带通信、雷达和测试仪器领域的应用需求,提出一种E波段宽带高中频(IF)单平衡混频器。射频(RF)及本振(LO)信号通过多分支宽带加宽波导正交耦合器输入,通过鳍线过渡结构将信号从波导传输模式过渡到微带模式,并提供宽带中频信号及直流接地回路;中频输出低通滤波器可有效抑制LO及RF信号,并为其提供等效接地回路。利用肖特基二极管的非线性实现混频,并通过微带匹配电路最终实现宽带低损耗混频效果。混频器采用57.6、62.4、67.2 GHz 3个点频本振,将67~85 GHz的射频信号分段下变频至9.4~17.8 GHz的中频范围内。测试结果表明,在67~85 GHz射频频率范围内,射频输入功率为-15 dBm,本振输入功率为12 dBm时,混频器变频损耗为7.1~10.1 dB,对组合杂散的抑制在36 dBc以上。     

双频段低噪声放大器的设计

适应多标准移动通信终端的迅速发展,设计了能够在800 MHz和1.8 GHz两个不同频段独立工作的低噪声放大器.放大器使用噪声性能优良的SiGeHBT管子,采用Cascode结构减小Miller电容的影响,发射极串联电感消除放大器输入端噪声系数和功率匹配的耦合,输入匹配电路采用单通道串并联LC电路,计算串并联电感和电容值,可以在两个工作频点发生谐振.输出端通过调整负载阻抗到50Ω,采用简单的电路实现功率输出.ADS的仿真结果表明,本文设计的低噪声放大器在800MHz和1.8 GHz两个工作频段的S21分别达到了24.3 dB和21.3 dB,S11均达到了-13 dB,S22均在-27dB以下,两个频段的噪声系数分别为3.3 dB和2.0 dB.     

A full W-band low noise amplifier module for millimeter-wave applications

A full W-band Low Noise Amplifier (LNA) Module is designed and fabricated in this letter. A broadband transition is introduced in this module. The proposed transition is designed, optimized based on the results from numerical simulations. The results show that 1 dB bandwidth of the transition ranges from 61 to 117 GHz. For the purpose of verification, two transitions in back-to-back connection are measured. The results show that transmission loss is only about 0.9-1.7dB. This transition is used to interface integrated circuits to waveguide components. The characteristic of the LNA module is measured after assembly. It exhibits a broad bandwidth of 75 to 110 GHz , has a small signal gain above 21 dB. The noise figure is lower than 5dB throughout the entire W-band (below 3 dB from 89 to 95GHz) at a room temperature. The proposed LNA module exhibits potential for millimeter wave applications due to its high small signal gain, low noise, and low dc power consumption     

应用于2.4GHz无线传感网的低功耗共栅低噪声放大器设计

本文给出一种基于TSMC 0. 18μm RF CMOS工艺、应用于无线传感器网络2.4GHz的低功耗低噪声放大器设计。本设计采用两级级联的交叉耦合共栅结构,第一级共栅级采用电容交叉耦合技术以降低电路功耗的同时提高电路增益、降低电路噪声。第二级共栅级采用正反馈交叉耦合技术以提供一个负阻抵消负载电感的寄生电阻,提高电感等效Q值,进一步提高增益。为了达到足够的增益,作者设计了一款片上差分电感作为负载,对其进行了电磁场仿真,建立了双π模型并进行了流片验证。该低噪声放大器经过流片,测试结果显示：高增益工作情况下,其增益S21为16.8dB,低增益工作情况下为1dB。高增益工作情况下,其噪声系数为3.6dB;低增益工作情况下,电路的输入1dB压缩点为-8dBm,IIP3为2dBm。该低噪声放大器在1.8V电源电压下,工作电流约为1.2mA。     

基于噪声抵消技术的低功耗C频段差分低噪声放大器

设计了一款"基于噪声抵消技术的低功耗C频段的差分低噪声放大器。该放大器由输入级、放大级以及输出缓冲级3个模块构成,其中输入级采用电容交叉耦合的差分对与直接交叉耦合结构差分对级联,实现输入匹配及噪声抵消;放大级采用具有电阻-电感并联反馈的电流复用结构来获得高的增益、良好的增益平坦性及低的功耗;输出缓冲级采用源跟随器结构,实现良好的输出匹配。基于TSMC 0.18μm CMOS工艺库,验证表明在C频段,放大器的增益为20.4设计了一款??基于噪声抵消技术的低功耗C频段的差分低噪声放大器。该放大器由输入级、放大级以及输出缓冲级3个模块构成,其中输入级采用电容交叉耦合的差分对与直接交叉耦合结构差分对级联,实现输入匹配及噪声抵消;放大级采用具有电阻-电感并联反馈的电流复用结构来获得高的增益、良好的增益平坦性及低的功耗;输出缓冲级采用源跟随器结构,实现良好的输出匹配。基于TSMC 0.18 μm CMOS工艺库,验证表明在C频段,放大器的增益为20.4??0.5 dB,噪声系数介于2.3~2.4 dB之间,输入和输出的回波损耗均优于-11 dB,稳定因子恒大于1,在6.5 GHz下,1 dB压缩点为-16.6 dBm,IIP3为-7 dBm,在2.5 V电压下,电路功耗仅为6.75 mW。     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

1MHz～40GHz超宽带分布式低噪声放大器设计

为满足宽带系统中低噪声放大器(LNA)宽带的要求,采用0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,设计了两款1 MHz^40 GHz的超宽带LNA,分别采用均匀分布式放大器结构及渐变分布式放大器结构,电路面积分别为1.8 mm×0.85 mm和1.8 mm×0.8 mm。电磁场仿真结果表明,1 MHz^40 GHz频率范围内,均匀分布式LNA增益为15.3 dB,增益平坦度为2 dB,噪声系数小于5.1 dB;渐变分布式LNA增益为14.16 dB,增益平坦度为1.74 dB,噪声系数小于3.9 dB。渐变分布式LNA较均匀分布式LNA,显著地改善了增益平坦度、噪声性能和群延时特性。     

利用噪声抵消技术设计低噪声放大器

采用ADS软件设计并仿真了一种应用于WiMax2标准的低噪声放大器。该低噪声放大器基于TSMC 0.13μmCMOS工艺,工作带宽为2.3 GHz~2.7GHz。在电路设计中采用噪声抵消技术降低CMOS管的电流噪声。使用共栅极结构进行输入匹配,使用电容进行输出匹配。偏置电路采用电流镜原理。使用ADS2006软件进行设计、优化和仿真。仿真结果显示,在2.3 GHz~2.7GHz带宽内,放大器的电源电压在1.2V时,噪声系数低于1.96dB,增益大于21.8dB,整个电路功耗为9mW。     

一种24 GHz CMOS功率放大器设计

基于130 nm互补金属氧化物半导体(CMOS)工艺,设计了一种高增益和高输出功率的24 GHz功率放大器。通过片上变压器耦合实现阻抗匹配和功率合成,有效改善放大器的匹配特性和提高输出功率。放大器电路仿真结果表明,在1.5 V供电电压下,功率增益为27.2 dB,输入输出端回波损耗均大于10 dB,输出功率1 dB压缩点13.2 dBm,饱和输出功率17.2 dBm,峰值功率附加效率13.5%。     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

0.3～8GHz超十倍频程MMIC低噪声放大器设计

为应对未来射电天文发展对超过十倍频程带宽接收性能的需求,实现厘米波多波段同时观测,使用法国OMMIC公司70 nm GaAs mHEMT工艺研究并设计一款工作频率为0.3～8 GHz的超宽带单片微波集成低噪声放大器芯片.放大器电路采用三级级联放大结构,双电源供电,芯片尺寸为2000μm×1000μm.仿真结果显示,常温...