包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Ni纳米晶制备及其在MOS电容中存储特性研究

优化了Ni纳米晶的制备工艺参数,得到了分布均匀,形状为球形,平均尺寸5nm,密度2×1012/cm2的Ni纳米晶。在此基础上,制备了包含Ni纳米晶的MOS电容结构。利用高频电容-电压(C-V)和电导-电压(G-V)测试研究了其电学性能,证明该MOS电容结构的存储效应主要源于金属纳米晶的限制态。电容-时间(C-t)测试曲线呈指数衰减趋势,保留时间600s,具有较好的保留性能。     

Determination of recombination lifetime in MOS structures by a sine voltage-sweep technique

A sine-voltage technique for measurements of recombination lifetime in metal oxide semiconductor (MOS) structures is proposed. When a fast sine-voltage sweep ramp is applied to the gate of an MOS capacitor a non-equilibrium depletion layer is formed and electron–hole generation starts in the space–charge–region and in the bulk. If the measurements are performed at elevated temperature so that quasi-neutral region generation rather than space charge region generation dominates, then the diffusion length, consequently the recombination lifetime, can be determined.     

Correlation between oxide breakdown and defects in SiC wafers

A correlation between gate oxide breakdown in metal oxide semiconductor (MOS) capacitor structures and structural defects in SiC wafers is reported. The oxide breakdown under high applied fields, in the accumulation regime of the MOS capacitor structure, is observed to occur at locations corresponding to the edge of bulk structural defects in the SiC wafer such as polytype inclusions, regions of crystallographic misorientation, or different doping concentration. Breakdown measurements on more than 50 different MOS structures did not indicate any failure of the oxide exactly above a micropipe. The scatter in the oxide breakdown field across a 10 mm × 10 mm square area was about 50%, and the highest breakdown field obtained was close to 8 MV/cm.     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Improved ESD properties by combining GaN-based light-emitting diode with MOS capacitor

An InGaN/GaN light-emitting diode (LED) combined with a metal–oxide semiconductor (MOS) capacitor has been fabricated for high electrostatic discharge (ESD) protection. By connecting a MOS capacitor in parallel with the GaN-based LED, a level of defense against the ESD is significantly strengthened from 200 to 1900 V of human body mode (HBM), which corresponds to 6- to 7-fold enhancement in the ESD robustness of LEDs.     

Mechanism of positive charge generation in the bulk of HfAlO/SiO2 stack

We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/silicon dioxide (SiO₂) dielectric stack (equivalent oxide thickness = 2.63 nm) in metal–oxide–semiconductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model.     

Charging effect of Si nanocrystals in gate oxide near gate on MOS capacitance

MOS structure with Si nanocrystals embedded in the gate oxide close to the gate has a much larger capacitance compared to a similar MOS structure without the nanocrystals. However, charge trapping in the nanocrystals reduces the capacitance dramatically, and after most of the nanocrystals are charged up the capacitance is much smaller than that of the MOS structure without nanocrystals. An equivalent-capacitance model is proposed to explain the phenomena observed.     

A metal-oxide-semiconductor varactor

CMOS technology scaling opens up the possibility of designing variable capacitors based on a metal oxide semiconductor structure with improved tuning range and quality factor. This is due to an increase in the oxide capacitance and a reduction in the parasitic resistance. A prototype metal-oxide-semiconductor (MOS) variable capacitor of 3.1 pF nominal value has been realized in a 0.35-μm standard CMOS process. A factor two capacitance change has been achieved for a 2-V variation of the controlling voltage. The varactor Q ranges from 17 to 35, at 1.8 GHz     

The Effect of the Ionizing Radiation Intensity on the Response of MOS Structures

Semiconductors - The effect of the intensity of ionizing radiation on the volume charge and surface-state density of metal—oxide—semiconductor (MOS) structures with thin gate silicon...     

Transformerless capacitive coupling of gate signals for seriesoperation of power MOS devices

A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each metal oxide semiconductor field effect transistor (MOSFET), except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage division across the network of device capacitance and inserted capacitances triggers the entire series stack reliably. Design formulas are presented and simple circuit protection is discussed. Simulation shows reliable operation and experimental verification is presented, Application of the method is applied to series insulated gate bipolar transistors (IGBTs)     

高温氧化对SiC MOS器件栅氧可靠性的影响

SiC金属氧化物半导体(MOS)器件中SiO2栅氧化层的可靠性直接影响器件的功能.为了开发高可靠性的栅氧化层,将n型4H-SiC (0001)外延片分别在1 200,1 250,1 350,1 450和1 550℃5种温度下进行高温干氧氧化实验来制备SiO2栅氧化层.在室温下,对SiC MOS电容样品的栅氧化层进行零时击穿(TZDB)和与时间有关的击穿(TDDB)测试,并对不同干氧氧化温度处理下的栅氧化层样品分别进行了可靠性分析.结果发现,在1 250℃下进行高温干氧氧化时所得的击穿场强和击穿电荷最大,分别为11.21 MV/cm和5.5×10-4 C/cm2,势垒高度(2.43 eV)最接近理论值.当温度高于1 250℃时生成的SiO2栅氧化层的可靠性随之降低.     

Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

n metal oxide semiconductor (MOS)capacitors fabricated by the former method, which are much better than 4.6 Ⅴ and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Inversion charge modeling

A simple, implicit, relation for the inversion charge density in the channel of metal oxide semiconductor (MOS) transistors is presented. The relation is continuous and covers the whole operating range, from subthreshold to strong inversion. The derivative of the local inversion charge density with respect to the channel voltage is a simple expression in the charge density, leading to analytic integrals as required for obtaining the drain current and the capacitance coefficients     

Analog switch device using a MOS structure

The development and performance of an analog switch device is presented. The device is based in a metal–oxide–semiconductor (MOS) structure to control the current flow between two terminals, called drain and source. This current is controlled modulating the space charge region width of the MOS structure. Applying a gate voltage the SCR width is increased to a value larger than the theoretical one, this is due to the leakage current existence through the oxide. This oxide characteristic was obtained depositing the film by Atmospheric Pressure Chemical Vapor Deposition (APCVD) at 125 °C. The theoretical and experimental results are presented.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.     

An analysis and experimental approach to MOS controlled diodesbehavior

The metal oxide semiconductor (MOS)-controlled diode (MCD) is a new class of power semiconductor diode that can achieve ideal diode performance. In this paper, experimental verification of the MCD key concept is presented for the first time by using commercially available power metal oxide semiconductor field effect transistors (MOSFETs) operating as MCDs. Measurements of the reverse recovery currents and reverse recovery charges of these “MCDs” are obtained and compared with the body diodes of the MOSFETs. These measurements suggest that MCDs can reduce the reverse recovery current, storage charge, and switching loss significantly. Optimized MCD performances at 1.2 kV, 2.4 kV, and 4.5 kV are also predicted based on numerical simulations. Ideal performance of the MCD close to that predicted by the device simulation should be obtained once an optimized MCD is developed     

Nonvolatile memory characteristics of metallic nanodots as charge-storage nodes

The charge and discharge properties of NiSi nanodots in the gate oxide of MOS and MOSFET devices were investigated in order to utilize as the charge-storage nodes in a nonvolatile floating-gate memory. NiSi nanodots were formed by sputtering Ni and successive exposing to SiH₄ gas. The memory characteristics of MOS and MOSFET devices which contain the NiSi nanodots in the gate oxide were obtained through the capacitance-voltage measurements and the transient threshold voltage shift measurements. The window of threshold voltage shift was achieved to be 2.5 V when the gate bias voltages of ±20 V were applied for 1 s and 500 ms, respectively. The retention time of MOSFET memory-cell was estimated to be about 10 years.