电流模降压变换器抗干扰电流采样电路设计

A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented. Based on the widely-used traditional current-sensing structure, anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit. Also the transient response is faster through the introduction of current offset. The circuit is concise, simple to implement and suits for SoC applications with single power supply. A dualoutput current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5 μm CMOS process for validation. In the 2.5–5.5 V input range, the two channels work steadily in the load current range of 0–600 mA. And the measured maximum efficiency is up to 96%.     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.     

A new CMOS realization of a four terminal floating nullor (FTFN)

A novel circuit configuration for the realization of a four terminal floating nullor in CMOS technology is proposed. The circuit proposed combines the advantages of a cascade of common-source and common-gate amplifiers and a floating current source. PSPICE simulations show that the proposed circuit is suitable for wideband, accurate and wide dynamic range current-mode signal processing. The feasibility of the circuit is also tested successfully in a current-mode band-pass filter structure.     

CMOS FTFN realisation based on translinear cells

A novel CMOS implementation of a four-terminal floating nullor (FTFN) is proposed. The presented FTFN circuit is based on two translinear cells and cascode current mirrors. It provides an alternative solution to differential amplifier-based FTFN circuits. Simulation results show that the proposed circuit is quite suitable for wideband, accurate and wide dynamic range current-mode signal processing. The feasibility of the circuit is tested on a current-mode bandpass filter structure     

Algorithmic analogue-to-quaternary convertor circuit using current-mode CMOS

A new current-mode CMOS algorithmic analogue-to-quaternary data convertor circuit has been realised in a standard polysilicon-gate CMOS technology. This circuit accepts an analogue current input and develops a set of quaternary, base-four, output currents. A single type of convertor cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits.<>     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准对CATA和PTAT电流求和的思想．提出一种具有低温漂系数、高电源抑制比（PSRR）的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调。该基准源基于CSMC0．5μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路。使整个电路的电源抑制比在低频时达到122dB,温度系数（TC）在0-100℃的温度范围内约7ppm／℃。     

一款电流型控制的DC／DC降压转换器

本文提出一种新型电感电流检测电路,该检测电路不需要一个放大器作为电压镜像,从而使用的器件更少,功耗更低。该电感电流检测电路应用于DC／DC降压转换器,采用CSM 0．18μm CMOS工艺进行设计和仿真,仿真结果显示该电感电流检测电路的精度可达到96％,输出电压的纹波仅为1mV。     

High-speed and high-precision current winner-take-all circuit

A CMOS high-performance current-mode winner-take-all circuit is presented. The circuit employs a novel technique for inhibitory and excitatory feedbacks based on input currents average computation, achieving both high speed and high precision. The circuit is designed for operation with a wide range of input current values, allowing its integration with circuits operating both in subthreshold and in strong inversion regions. Two circuits, each for a different range of input currents, have been implemented in a standard 0.35-/spl mu/m CMOS process available through MOSIS and are operated via a 3.3-V supply. Their operation is discussed, simulation results are reported and preliminary measurements from a test chip are presented.     

CMOS current-mode exponential-control variable-gain amplifier

A CMOS current-mode exponential-control variable-gain amplifier is presented. It consists of a first-order current-mode pseudo-exponential circuit and a current-mode multiplier. Based on the Taylor's series expansion, the pseudo-exponential circuit can be realised by MOSFETs in saturation. The proposed circuit has been fabricated in a 0.5 μm n-well CMOS process with a gain control range of 15 dB. The experimental results confirm the feasibility of the proposed variable-gain amplifier     

A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies

A 1-V integrated CMOS current-mode boost converter implemented in a standard 3.3/5-V 0.6-/spl mu/m CMOS technology (V/sub TH//spl ap/0.85 V), providing power-conversion efficiency of higher than 85% at 100-mA output current, is presented in this paper. The high-performance boost converter is successfully developed due to three proposed low-voltage circuit structures, including an inductor-current sensing circuit for current-mode operation with accuracy of higher than 94%, a precision V-I converter for compensation-ramp generation in current-mode control, and a VCO providing supply-independent clock and ramp signals. Moreover, a proposed startup circuit enables proper converter startup within a sub-1-V supply condition.     

一种新的应用于降压式DC-DC变换器电流采样电路的设计

在分析了传统的应用于大负载电流降压式DC-DC变换器电流采样电路主要缺点的基础上,提出一种新的应用于降压式DC-DC变换器的电流采样电路。该方法通过一个电阻电容网络来消除电感寄生电阻的影响,并利用开关电容积分器来实现降压式DC-DC变换器的电流采样,在Chartered 0.35μm CMOS工艺下实现该电路并流片验证。最终的测试结果显示,提出的电流采样电路实现了对降压式DC-DC变换器精确的电流采样。     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.     

A New Monolithic Fast-Response Buck Converter Using Spike-Reduction Current-Sensing Circuits

A new monolithic fast-response buck converter using spike-reduction current-sensing circuits is proposed in this paper. The proposed converters are designed and implemented with TSMC 0.35-mum DPQM CMOS processes. The operation frequency can be up to 1.887 MHz. The response time is only 2 mus and compared with other references. The maximum output current is 750 mA, and the maximum power efficiency can be up to 89.1% at 2.442-W output power. The chip area is only 2.157 mm².     

A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA

This paper proposes a circuit to linearize the signal current and improve the distortion characteristics at the input of a current-mode circuit. Input voltage-to-current (V/I) conversion is carried out by a resistor that connects the signal source and the current input terminal of the current-mode circuit. The signal current flowing into the current-mode circuit through this resistor is distorted because of the signal-dependent voltage change at the current input terminal, and it is linearized by injecting a current that is proportional to the signal-dependent voltage change at the current input terminal, into the same current input terminal of the current-mode circuit. A current-mode sample-and-hold amplifier (SHA) that adopts the proposed scheme was fabricated and a 0.35-$mu{hbox {m}}$ CMOS process was used to verify the effectiveness of the scheme. It operated from a 2-V supply voltage in the analog part and a 2.5 V in the digital part with a 100-MHz clock and realized a 77- and a 86-dB spurious-free dynamic range values for 0 and $-$10 dB of full-scale signal current level $(pm hbox{100} mu{hbox {A}})$, respectively, of the 1-MHz signal input. More than a 13-bit equivalent SFDR for $-$14 to $-$4 dB of full-scale input was obtained, proving the effectiveness of the proposed scheme at realizing distortionless signal current processing.      

基于跨导放大器的电流模式积分单元的设计

在集成电路系统中,各种模拟功能的电流单元都是由基本的电流模单元组成。跨导放大器是电流模电路的基本单元。基于跨导放大器的电流模积分器可以实现电流到电流的积分转换。同时可应用于各种集成滤波电路的设计。在此采用0．18ptmCMOS仿真工艺,使用共源共栅结构设计一款供电电压为1．8V的高增益低功耗的跨导放大器,采用具有PTAT基准电流源的偏置电路,使用HSpice进行优化设计,并将此放大器应用于电流模式积分单元的电路仿真。     

Current-mode pseudo-exponential circuit with tunable input range

A current-mode pseudo-exponential circuit is presented based on Taylor's series expansion. It is composed of MOS transistors operating in saturation and its input range can be tuned by adjusting the biased current. The proposed circuit has been verified in 0.8 μm CMOS technology by HSPICE simulations. The simulation results confirm the feasibility of the proposed pseudo-exponential circuit     

CMOS Current-Mode Implementation of Fractional-Power Functions

A CMOS current-mode circuit, with only eight transistors and two current sources, is proposed to implement a fractional power function. The compact circuit comprises of an approximating logarithm circuit and an approximating exponential circuit. By sizing one transistor and tuning one current source, we improve the truncation errors in the Taylor series approximation, and reduce the MOS square-law errors that are caused by second-order effects. As example, a circuit, designed for gamma correction, with different gamma values controlled by three switches, is fabricated using 0.35 μm CMOS technology. The demonstration circuit can achieve a bandwidth of 155 MHz for an input range from 40 μA to 130 μA with 3% error, and maximum power dissipation of approximately 970 μW.     

降压变换器片内集成软启动电路设计

针对电流模降压变换器的集成化趋势,提出了一种可片内集成的软启动电路. 该结构利用芯片振荡器产生的窄脉冲信号,控制微电流对片内电容间歇充电得到斜坡电压,并巧妙地利用复合比较器以较小的功耗实现了对峰值电流的限制,避免了浪涌电流,完成了软启动功能. 提出的软启动电路结构简单、易于实现,减少了芯片引脚数目,降低了PCB面积,并在一款基于0.5μm CMOS工艺设计的降压型DC-DC中进行了投片验证. 测试结果表明,3.6V输入1.8V输出600mA负载电流在使能140μs后芯片成功实现了软启动.