一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

GaAs TUNNETT diodes oscillating at 430-655 GHz in CW fundamental mode

GaAs TUNNET diodes with 75-nm thick undoped transit-time layer and 14-nm thick n/sup +/ electric-field-inducing layer were fabricated with molecular layer epitaxy. They were oscillating in fundamental-mode metal rectangular resonant cavities of WR-1.5 (0.381 /spl times/ 0.191 mm) and WR-1.2 (0.305 /spl times/ 0.152 mm) types. Continuous wave generation of -53 dBm to -49 dBm, in the frequency range of 430-510GHz, at the bias current from 500 to 560 mA was obtained in the WR-1.5 cavity. In the WR-1.2 cavity, CW generation in the range of 571-655 GHz was obtained with the bias current changing from 460 to 540 mA. Output power was -61dBm at 655 GHz. Frequency range of CW fundamental-mode TUNNETT diodes fabricated with molecular layer epitaxy extends from 60 GHz (+13 dBm) to 655 GHz.     

A 90 nm CMOS 15/60 GHz frequency quadrupler

The design and characterisation of a 60?GHz frequency quadrupler implemented in a conventional 90?nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15?GHz to 30?GHz doubler, two 30?GHz amplifiers, a polyphase filter, a 30 to 60?GHz doubler and two 60?GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3?dBm at 60?GHz with 1.1?dBm input power is achieved. The 3?dB bandwidth lies between 51.5?GHz and 61?GHz, while the total current consumption is 100?mA from a 1.2?V supply voltage for the fully balanced implementation.     

26-34 GHz CMOS mixer

A 26-34 GHz fully integrated CMOS down mixer is presented. At 30 GHz RF frequency and 2.5 GHz IF frequency, 50 /spl Omega/ terminations, 5 dBm LO and 1.2 V/spl times/17 mA supply power, the circuit yields a conversion loss of 2.6 dB, an SSB NF of 13.5 dB and an IIP3 of 0.5 dBm.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90^deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.     

60 GHz amplifier employing slow-wave transmission lines in 65-nm CMOS

A three-stage V-band amplifier implemented in 65-nm baseline CMOS technology is presented in this paper. Slow-wave coplanar waveguides are used for matching and interconnects to study the benefits of using this line type in amplifier design. Measured power gain, noise figure and 1 dB output compression point at 60 GHz are 13 dB, 6.3 dB and +4 dBm, respectively. The amplifier has 19.6 GHz of 3 dB bandwidth, thus covering entirely the unlicensed band around 60 GHz. The performance is achieved with a 1.2 V supply and 45 mA DC current consumption.     

Monolithic SiGe HBT Feedforward Variable Gain Amplifiers for 5 GHz Applications

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled‐emitter resistor and the other using an HBT‐based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain‐control range of 23 dB with a control‐voltage range from 0.4 to 2.6 V. The gain‐tuning sensitivity is 90 mV/dB. At V_CTRL= 2.4 V, the 1 dB compression output power, P_1‐dB, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and ‐1.8 dBm and 71mA in a VGA with a constant current source, respectively.     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

Monolithic 2-18 GHz low loss, on-chip biased PIN diode switches

Two state-of-the-art monolithic GaAs PIN diode switches have been designed, fabricated and tested. These single-pole double-throw (SPDT) switches exhibit insertion losses of 1.15±0.15 dB over a 2-18 GHz band, which is an unprecedented performance in loss and flatness for monolithic wideband switches incorporating on-chip bias networks. Isolation and return loss are greater than 43 dB and 12 dB, respectively, and the input port power handling is 23 dBm at 1-dB insertion loss compression. These performance characteristics were measured at a nominal bias setting of -8 V, which corresponds to 3.7 mA of series diode bias current and a total dc power consumption of 55 mW. The input power at the third-order interception is 40 dBm. The switches can handle up to 31 dBm (1.25 W) at a higher bias of -18 V and 9.3 mA     

A 100 MHz to 1 GHz Variable Gain Amplifier in a 8 GHz 1.2 µm BiCMOS Process

A variable gain amplifier with linear gain control has been implemented in a commercially available 8 GHz 1.2 µm BiCMOS process. The gain adjustment linearization is based on forcing a linearly controllable current through diode-connected transistors, thus generating an internal logarithmic control voltage for the Gilbert-type variable gain cell. A Cherry-Hopper type gain stage is used to provide most of the available gain. Thus, the maximum differential gain is 10 dB with over 1 GHz bandwidth and –6.9 dBm input –-1 dB compression power. Gain adjustment range of 50 dB at 200 MHz and 38 dB at 960 MHz is reported. The chip area is 1.15 × 2.15 mm and it consumes 40 mA from a 5 V supply.     

多模式卫星导航接收机中双频段LNA设计

设计出一款应用于多模式卫星导航接收机射频前端的双波段LNA,该电路可以工作在1.575GHz和1.267GHz两个波段附近,覆盖了当今各种卫星导航系统的载波频段.LNA的输入阻抗和输出阻抗均被匹配到50Ω,电路采用0.18μmCMOS工艺实现.测试结果表明该电路在1.575GHz和1.267GHz两个波段上噪声系数分别为0.88dB和0.78dB,功率增益分别为25.5dB和25.9dB,S11分别为-16dB和-12.5dB,1dB压缩点分别为-23.4dBm和-23.6dBm,1.8V供电电压条件下静态工作电流均为4.0mA.电路在上述两个频段上稳定性均满足要求.     

A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter

This paper presents a folded-cascode mixer for an ISM band transmitter that translates the signals at the 2.4 GHz band to 5.8 GHz. Comparing to the conventional Gilbert cell mixer, our proposed folded-cascode mixer architecture with DC offset blocking, and transconductance linearization techniques can effectively suppress the LO feedthrough by 9 dB. The proposed mixer is designed in 0.11 μm CMOS and consumes 2.6 mA from a 1.2 V supply. The simulation results show that the mixer achieves an output power of 4.7 dBm, and all the emission spurs are well below −40dBc.     

High-Power High-Linearity Uni-Traveling-Carrier Photodiodes for Analog Photonic Links

We have fabricated and characterized two high-power high-linearity uni-traveling-carrier photodiode (UTC-PD) structures. The UTC performances are compared regarding their respective collector design. A -3-dB bandwidth improvement (from 16-25 GHz to 19-32 GHz) is achieved when the collector layer thickness is increased (from 250 to 350 nm, respectively). The bandwidth improvement for large photocurrent is at the origin of a ldquosupra-linearityrdquo effect. Photocurrent saturation effects are investigated and -1-dB compression current measurements at 20 GHz show saturation currents as high as 70 mA at -4 V. We also report third-order intermodulation distortion measurements at 20 GHz. The ldquosupra-linearityrdquo effect enhances the PD linearity with increased photocurrent, leading to a record third-order intercept point of 35 dBm at 40 mA.     

1.7 Volt, DC to 15 GHz Differential Amplifier with Constant Group Delay in InP-HBT Technology

10 dB gain–, 15 GHz-Bandwidth amplifier has been designed andfabricated in InP-HBT technology. Operation of the amplifier was achieved at1.7 V at total current consumption of 40 mA. The amplifier designed to havea Bessel-transfer-function has almost constant group delay up to 30 GHz.Pulse- and eye-diagram- measurements have been performed to verify largesignal operation. At 3.3 V, 24 dB gain and 10 GHz bandwidth was achieved.The 1dB compression point at 1.7 V supply voltage is measured at –10dBm output power.     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

Device characteristics of the GaN/InGaN-doped channel HFETs

First dc, small signal, and RF power characteristics of GaN/InGaN doped-channel heterojunction field effect transistors (HFETs) are reported. HFETs with a 1-μm gate length have demonstrated a maximum drain current of 272 mA/mm, a flat G_m around 65 mS/mm in a V _GS between -0.65 V and +2.0 V, and an on-state breakdown voltage over 50 V. Complete pinchoff was observed for a -3.5 V gate bias. Devices with a 1-μm gate length have exhibited an f_T of 8 GHz and f_max of 20 GHz. A saturated output power of 26 dBm was obtained at 1.9 GHz for a 1 μm×1 mm device     

用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2.4GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0.35μm CMOS工艺技术,在2V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3mA,输入三阶截距点达到20dBm,输出的信号幅度为87mV;下混频器消耗的电流为3.5mA,得到的转换增益是20dB,输入参考噪声电压是6.5nV/ Hz,输入三阶截距点为4.4dBm.