用于带有片上时钟的窄带低中频接收机的自适应数字校准技术

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.     

一种用于短距离器件的433/868 MHz的带I/Q校准的低中频接收机

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.     

A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of--60 dBm and a control gain of 60 dB. The S<,11> reaches-20 dB at 433 MHz and-10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm2 including the bias circuit.     

ADAPTIVE CALIBRATION OF I AND Q MISMATCH IN QUADRATURE RECEIVER

The mismatch of in-phase and quadrature channels in quadrature receiver affects and constrains radar detection performance in coherent radar.It is necessary to keep the in-phase and quadrature branches symmetrical.In this letter,an adaptive method to detect imbalance parameters is derived by means of evaluating channel errors from the received signal sequences.No matter how the bias degree of the gain and phase errors in I/Q channels are ,the proposed adaptive scheme can obtain good calibration results.And the required calculations are only a few multiplications and additions.No need of a special test signal,the introduced method is simple to implement and easy to operate.     

I/Q mismatch calibration based on digital baseband

A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only needs a calibration chain to detect mismatches and then transmit them to the digital baseband.Simulation results show that the calibrated errors of the proposed technique are less than 7%.The measurement results indicate the function of the proposed technique is correct,but the performance should be improved further.     

基于LS的OFDM零中频接收机IQ不平衡数字补偿技术

零中频接收机已成为未来无线终端发展潮流,但是零中频的结构会引入较大的射频损伤;本文首先介绍了射频I/Q不平衡时对高斯以及频率选择性信道下OFDM接收机性能的影响;通过特殊导频设计,解耦合I、Q路的相互影响;如此可以方便地估计和补偿射频I/Q不平衡对高斯以及频率选择性信道的影响。仿真表明本文所示方法大大提高了OFDM零中频接收机的性能。     

高速A/D转换器在宽带数字化接收机中的应用

高速A/D转换器是数字化接收机系统的重要组成部分。本文从系统的角度分析了A/D数字模块对接收机灵敏度、动态范围的影响,结合实际宽带数字接收系统进行了设计实现并给出了指标测试方法。     

OFDM零中频接收机I/Q不平衡的数字估计与补偿

由于零中频接收机的优点,其已经成为未来无线终端发展的方向.但它也有固有缺陷,即引入较大的射频损伤.首先分析了I/Q不平衡的系统模型,接着推导出其在OFDM系统中对接收机的影响.提出了一种硬件容易实现的简便时域估计和补偿I/Q不平衡的算法.最后通过仿真给出了该算法的性能,仿真表明在AWGN和频率选择性衰落信道下能够明显提高接收机的误码率性能.     

光接收机均衡技术的自适应优化方法

自适应技术是目前光通信研究热点之一的接收机均衡技术的重要组成部分.文章在简要介绍光接收机中常用的均衡处理技术的基础上,总结了应用较多的LMS等多种自适应均衡算法的基本形式,并对目前有关算法在光通信中应用的研究结果及多种的算法改进进行了总结和分析,同时对与其紧密相关的反馈监测信号的选取等问题进行了对比分析.     

一种应用于无线局域网接收机的1.2伏双通道10位55nm CMOS流水线模数转换器

A power-efficient technique for pipeline analog-to-digital converters(ADCs) is proposed. By sharing amplifiers between I/Q channels, the power dissipation of the ADCs is reduced by almost one-half compared to conventional topologies, which makes this technique suitable for low-power direct-conversion WLAN receivers. A dual-channel ADC test chip is fabricated in 55 nm CMOS technology. The 10 bit ADC with on-chip reference generators dissipates 19.2 mW per channel from a 1.2 V supply. At an 80 MS/s sample rate, the measured spuriousfree dynamic range, signal-to-noise and distortion ratio, and corresponding effective number of bits are 69.5 dB, 56.8 dB and 9.14 bits with a 1 MHz input frequency(fin/, and 61.3 dB, 56.5 dB and 9.09 bits with a 15 MHz fin, respectively. The active area is 1.01 0.77 mm2.     

基于65nm CMOS用于导航接收机的2mW 50dB范围宽带混合AGC设计

实现了一种用于导航接收机的低功耗宽带混合自动增益控制(AGC)环路。I/Q路中单个AGC由四级可编程增益放大器(PGAs)、差分峰值检测、两个比较器、控制算法逻辑、译码器和参考电压源组成。除了能由AGC环路控制外,PGA的增益也能通过SPI接口由片外数字基带处理器控制。为获得低功耗和噪声,采用一种改进的源简并放大器,且I/Q路间的相位失配能以0.2?精度在?5?范围内校准。整体电路用65nm CMOS实现,测试的PGA总增益为9.8dB~59.5dB,平均步进为0.95dB,且仿真带宽超过110MHz。从射频放大器RFA输入端口加功率-76.7dBm~-56.6dBm跳变的80% AM信号,测试建立时间约为180μs,且随着时钟频率加倍减小到90μs。单个AGC用2.5V电源供电时消耗约0.8mA电流,占用750?300μm2芯片面积。     

带宽给定条件下的全数字接收机频率规划

本文分析了带宽给定条件下,全数字接收机中频频率与采样频率的约束关系;导出了采样频率给定条件下,使得数字滤波器过渡带宽最大的中频频率表达式.最后,本文以GPS P(Y) 码接收机频率规划为例给出了设计实例.     

采用数字辅助直流失调消除技术适用于WCDMA/GSM接收机的双模模拟基带

A dual-mode analog baseband with digital-assisted DC-offset calibration (DCOC) for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP₂ is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13 μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm².     

A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

A dual-mode analog baseband with digital-assisted DC-offset calibration(DCOC) for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm~2.     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

RF power and I/Q imbalance calibration in B3G/4G MIMO-OFDM systems

Radio frequency (RF) front-end nonidealities in multi-input and multi-output (MIMO) systems are more serious than in single-input and single-output systems and must be calibrated. According to the effects of RF power and in-phase/quadrature-phase (I/Q) imbalance, calibration methods for multi-input and multi-output-orthogonal frequency division multiplexing (MIMC-OFDM) systems in transmitter and interference in receiver are improved, respectively, in this article. Furthermore, a calibration scheme including I/Q imbalance errors and amplitude variations is proposed and implemented in the B3G/4G time division duplex communication system. Simulation results show that the calibration algorithms are feasible, and the bit error rate (BER) performances for MIMO-OFDM systems are improved after calibrations.     

基于CVI的数字示波器自动校准系统设计

以LabWindows/CVI为软件平台,利用VISA和SCPI命令开发完成数字示波器自动校准系统。该系统可快速完成基于GPIB,RS232,LAN接口的数字示波器的自动化校准,保存测试数据,并自动判定测试结果,同时通过ActiveX技术实现Microsoft Word校准证书的自动生成、打印和保存。系统可消除人工手动操作引入的误差,具有长时间工作的稳定性,保证了计量工作的一致性。该系统具有易扩展性,只需通过添加对应型号示波器的控制文件就可以支持新的数字示波器。     

一种应用于WLAN相位可调的本振缓冲器

该文提出了一种应用于WLAN相位可调的本振缓冲器,用于校准直接下变频收发机的I/Q两路不平衡。该电路通过开关输入MOS管源极的电容阵列,延迟本振信号,从而调节信号的相位。该文采用SMIC 0.18m工艺实现了4.8~6GHz的I/Q两路本振缓冲器的设计,其版图面积为650550m2。仿真结果表明,在5位控制字作用下,I或者Q路本振缓冲器的相移在0~8的范围内呈现近乎线性的变化,而本振缓冲器的输出功率的变化范围只有0.2dB。     

高频地波雷达交叉环/单极子天线幅度相位校准

针对小口径高频地波海态监测雷达广泛采用的交叉环/单极子天线阵列,理论分析了接收通道幅度和相位误差对其到达角估计精度的影响.由于常规线性拟合估计增益误差的方法常常失效,为此提出了更实用的校正方法:在单极子上预选出大信噪比谱点作为候选校正谱点,再根据天线共相位中心约束条件作进一步筛选,由单极子和交叉环上各谱点的互协方差估计出相位误差,并由归一化谱功率比估计出幅度误差.该方法在便携式高频地波雷达OSMAR-S中运行良好.现场比测实验结果证明了该方法的有效性.