A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator(DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18μm CMOS process with six metal layers.A third new way to change capacitance is proposed and implemented in this work.Results show that the phase noise at 1 MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also,the DCO can work at low supply voltage conditions with a 1.6 ...     

低电压环形振荡器设计

提出了一种新的两级环形振荡器结构，通过控制PMOS的衬底电压，来降低PMOS管的阈值电压，从而使新的环形振荡器可以在低电压下工作到很高的频率。仿真结果表明，在电源电压为1V，调节电压在0～1V范围内变化时，振荡器的频率为300MHz-4GHz。     

Design of 10 GHz eight-phase voltage controlled oscillator in 90 nm CMOS

A novel 10 GHz eight-phase voltage-controlled oscillator(VCO) architecture applied in clock and data recovery(CDR) circuit for 40 Gbit/s optical communications system is proposed.Compared with the traditional eight-phase oscillator,a new ring CL ladder filter structure with four inductors is proposed.The VCO is designed and fabricated in IBM 90nm complementary metal-oxide-semiconductor transistor(CMOS) technology.Measurement results show the tuning range is 9.2 GHz～11.0 GHz and the phase noise of-108.85 dBc/Hz at 1 MHz offset from the carrier frequency of 10 GHz.The chip area of VCO is 500 μm× 685 μm and the power dissipation is 17.4 mW with the 1.2 V supply voltage.     

宽频率范围的单子带压控振荡器设计

基于TSMC 180 nm CMOS工艺,提出了一种振荡频率为2～3 GHz的宽频率范围、低相位噪声的单子带压控振荡器(VCO).采用双平衡吉尔伯特混频结构,将单子带5～6 GHz压控振荡器与固定频率3 GHz压控振荡器进行下混频,可得到振荡频率为2～3 GHz的单子带压控振荡器,实现相对带宽从18.18％到40％的展...     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

A low-phase-noise 900-MHz CMOS ring oscillator with quadrature output

A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW.     

一种带高阶温度补偿的片内时钟振荡器设计

本文基于0.18μm CMOS工艺,设计了一款适用于片上系统SoC的无需晶振的片内12MHz时钟信号产生电路。利用高阶温度补偿方案,该时钟振荡器能在较宽的温度范围内实现振荡频率的高稳定性。此外,电路的稳压器设计使得振荡器频率在电源电压变化时也能保持相当好的稳定性。仿真结果表明,在-40℃~125℃温度范围内,此振荡器振荡频率的温度系数仅为40ppm/℃,电源电压变化±10%时,振荡频率的相对误差仅为±0.012%,完全能够满足常规数字系统的要求。     

High frequency dividing synchronous oscillator using modified emitter couple logic inverters

A synchronous oscillator using a high speed low-voltage emitter coupled logic (ECL) inverter has been reported. Using the positive feedback the locking range increases, compared to the oscillator without any positive feedback. A maximum improvement (increase) of percentage locking range of around 105% was obtained from circuit simulation as well as from practical circuit, using discrete components. Because the locking range is maximum at double the output frequency of the oscillator, this oscillator can be used as a high frequency divider circuit. The circuit requires a supply voltage of 2.1 V.     

A C-band low-power sub-1volt current-reused multiphase oscillator

A new sub-1V and low power multiphase voltage-controlled oscillator (QVCO) with current-reused structure is proposed. The proposed core oscillator consists of two N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors and an additional NMOS-only cross-coupled pair that enhances the effective negative transconductance and facilities the start-up condition at sub-1V supply voltages in modern nm CMOS technologies. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling in an ‘in-phase−anti-phase’ manner. Parallel capacitors to the drain-source of transistors have been used for further enhancement of effective transconductance and thus lower power consumption; though the increase of parallel capacitors reduces the tuning range, indicating a trade-off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated in a standard 0.18 μm RF-CMOS technology. The results of the simulation show that the QVCO has a 9% tuning range from 5.35 GHz to 5.88 GHz, and the phase noise is −119.6 dBc/Hz at 1-MHz offset from the 5.7 GHz carrier while consumes only 1.4 mW from a 0.85-V supply voltage; yielding an excellent figure-of-merit (FOM) of −193.3 dBc that is amongst the best FOMs. Several Monte Carlo and PVT analyses verify the robust performance of the QVCO.     

Improved memristor-based relaxation oscillator

This paper presents an improved memristor-based relaxation oscillator which offers higher frequency and wider tunning range than the existing reactance-less oscillators. It also has the capability of operating on two positive supplies or alternatively a positive and negative supply. Furthermore, it has the advantage that it can be fully integrated on-chip providing an area-efficient solution. On the other hand, The oscillation concept is discussed then a complete mathematical analysis of the proposed oscillator is introduced. Furthermore, the power consumption of the new relaxation circuit is discussed and validated by the PSPICE circuit simulations showing an excellent agreement. MATLAB results are also introduced to demonstrate the resistance range and the corresponding frequency range which can be obtained from the proposed relaxation oscillator.     

Class E Colpitts oscillator for low power wireless applications

A class E Colpitts oscillator for low power wireless applications, operating around 900 MHz, is reported for the first time. A microstrip design of the oscillator demonstrates a maximum drain efficiency of 46.5%, with an output power of 8.5 dBm, at a supply voltage of 1.2 V. Simulation predicts that a miniaturised design of the oscillator with lumped element components would achieve a drain efficiency of over 60%.     

RS trigger based relaxation oscillator for temperature measurement circuit

Resistance-to-time converter is always used for digital temperature measurement. An reset-set （RS） trigger based, relaxation oscillator based temperature measurement circuit, which is used to convert the change of thermistor sensor into a frequency signal for later processing, has been presented in this article. The RS trigger, which is composed of two inverters designed with distinct logical transition threshold voltages by changing the metal-oxide-semiconductor （MOS） transistor gains, has the same function as the Schmitt trigger in the relaxation oscillator. The advantage of the RS trigger based Schmitt trigger is that it reduces the dependence to supply voltage, chip temperature, and process variation. This temperature measurement circuit has been applied in a clinical thermometer chip that can measure temperature to an accuracy of better than 0.05 ℃ down to 1.1 V battery voltage. It is fabricated in 0.5 μm double metal single poly complementary MOS （CMOS） process.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology for UWB applications

In millimeter wave systems, performance degradation mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for ultra-wide band applications identified for possible 5G usage. For this purpose, a novel differential symmetrical load delay cell based 3-stage ring oscillator has been introduced to design the ring-VCO. The 28 nm CMOS Fully Depleted Silicon On Insulator (FDSOI) technology is adopted for designing this VCO circuit with 1 V power supply while a new voltage control through the transistor body bias is implemented. The simulated results show that the proposed oscillator works in the tuning range of 29–49 GHz and dissipates 3.75 mW of power. It exhibits a phase noise of −129.2 dBc/Hz at 1 MHz offset from 49 GHz oscillation frequency, and a remarkable Figure of Merit (FoM) of −217.26 dBc/Hz. With similar power supply, the phase noise rises to −93.16 dBc/Hz for a second oscillator involving more of active components exactly 9 delay cells. Further, the impact of the operation temperature variation on the VCO performance is investigated. Results show a drift in the oscillation frequency for a temperature step from 27 °C to 40 °C and a degradation of 3dBc in the phase noise performance.     

A 1.2- mu m CMOS current-controlled oscillator

A simple, fully symmetrical, current-controlled CMOS oscillator is presented. The oscillator uses two grounded capacitors. This 5-V architecture permits relatively large capacitor voltage amplitudes, thus minimizing jitter. The design also operates with power supply voltages as low as 3 V. Because there are no special capacitor requirements, the design is compatible with standard scaled digital CMOS processes. The use of a double differential latching comparator allows high-speed operation with good control linearity. The circuit was successfully fabricated using a 1.2- mu m CMOS process.<>     

A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners

This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator(DCXO) with automatic amplitude control(AAC).The DCXO is based on Colpitts topology for one-pin solution.The AAC circuit is introduced to optimize the phase noise performance.The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array,ensuring a～35 ppm tuning range and～0.04 ppm frequency step.The measured phase noise results are-139 dBc/Hz at 1 kHz and-151 dBc/Hz at 10 k...     

5 GHz quadrature voltage-controlled oscillator using trifilar transformers

A 0.18 mum CMOS 5 GHz quadrature voltage-controlled oscillator (QVCO) is demonstrated by using trifilar transformer coupling. The trifilar transformers composed of one primary coil and two secondary coils are used to separate the gate and drain bias for output voltage swing optimisation and also replace a conventional transistor-coupling method for quadrature output generation simultaneously. As a result, the trifilar-coupling QVCO achieves 180.1 dBc/Hz figure of merit (FOM) at the supply voltage of 1.2 V. The on-chip passive single sideband upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Thus, a 33.7 dB sideband rejection ratio is achieved.     

CMOS ring oscillator with combined delay stages

Full transistor voltage control oscillators by delay stages are studied in this paper. First we describe the general conditions of oscillators and after introducing some common inverters, calculating their delay times, we analyze the dependence of delay time to variation of power supply voltage. The analyzing results show that the delay of basic type inverter varies in the opposite direction as that of current starved inverter, therefore to achieve better frequency stability versus voltage power supply changing, some combined structures of inverters are presented. The results of simulation by 0.18 CMOS technology library of HSPICE approve the analysis results.     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

A cross coupled low phase noise oscillator using an output swing enhancement technique

A new voltage controlled oscillator (VCO) in a 0.18 μm CMOS process is offered in this paper. This paper?s argument is to provide an innovative approach to improve the phase noise which is one of the most controversial issues in VCOs. Contrary to most ideas that have been put forward to decrease phase noise which are based on higher current dissipation to increase output voltage swing, this new method offers better specifications with respect to traditional solutions. The presented circuit is capable of extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the presented peak voltage amplitude can verify the optimum performance of the proposed. Post-layout simulation results at 2.3 GHz with an offset frequency of 1 MHz and 3 MHz show a phase noise of about −125 dBc/Hz and −136.5 dBc/Hz, respectively, with the current of 1.3 mA from 1.8 V supply. Also, Monte Carlo simulation is used to ensure the sensitivity of the proposed circuit to process and frequency variations are very promising.