一种应用于DRM/DAB调谐器的低噪声及dB线性中频可变增益放大器设计

A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S_(11) of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.     

一种应用于DRM/DAB/DVB-H的噪声抵消和IP3改进的CMOS射频前端设计

本文给出了一种应用于数字广播标准的CMOS射频前端电路芯片,其包括宽带低噪声放大器、正交混频器和可变增益放大器,该前端能够支持200kHz-2GHz频率范围内的多种无线通信标准,该电路在没有牺牲其他电路性能包括电压增益和功耗的情况下,改善了NF和IP3。通过噪声抵消技术降低前端的NF,通过差分多栅晶体管结构（DMGTR）提高前端的IP3。dB线性可变增益放大器的增益控制通过采用工作在线性区的PMOS晶体管来实现。芯片采用0.18um CMOS工艺实现。测试结果表明在200kHz-2GHz范围内S11小于-11.4,增益变化范围在250MHz为12-42dB,在2GHz为4-36dB。单边带NF为3.1-6.1 dB。在中等增益情况下IIP3为-4.7-2.0dBm。整个前端在1.8V电源电压情况下功耗仅仅为36mW。     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

DAB接收机中的低相位噪声低功耗高速数模混合下分频模块

本文实现了一种用于DAB数字广播调谐器的具有低相位噪声与低功耗的高速数模混编下分频模块。在设计中采用了若干项新的电路技术以提升电路的性能。采用了具有改进型源极耦合逻辑D触发器的同步分频器与具有改进型CMOS主从触发器的异步分频器实现了具有低相位噪声的双模分频器。在吞吐式计数器的设计中采用了一种更为精确的线负载模型。电路采用0.18-?m CMOS工艺实现。芯片面积为0.6mm?0.2mm。下分频模块中的双模分频器的输出信号在距载波中心频率10kHz频偏处的相位噪声仅为-118.2dBc/Hz。下分频模块的核心部分在1.8V供电电源下的功耗仅为2.7mW。     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

A CMOS linear-in-dB VGA and AGC loop for telecommunication applications

In this paper, an Automatic Gain Control (AGC) loop which is based on a linear-in-dB Variable Gain Amplifier (VGA) is proposed. The VGA structure is based on simple nMOS differential pairs with variable tail currents. The linear-in-dB gain tuning schema is designed using a novel exponential current generator which also offers temperature compensation of the VGA's gain. The gain of the VGA is tuned by a control voltage with gain range about 28 dB with ±1 dB linearity error. The worst cases of the VGA gain, over process and temperature corners, are ±1.54 dB and ±2.45 dB for maximum and minimum gain setting, respectively. The proposed implementation is designed in a CMOS 90 nm triple-well process with 1.2 V supply voltage.     

10 Gb/s 带有直流漂移校正的dB线性、无电感宽带可变增益放大器

本文介绍了一款带有直流漂移校正的dB线性、无电感宽带可变增益放大器。该可变增益放大器包含一个可变增益模块,一个带有共模电压调整的直流漂移校正模块,以及一个带宽拓展模块。为了放大器带宽同时节约芯片面积,本设计中带宽拓展模块采用了一种无电感设计的有源反馈技术,通过该模块在高频增益过冲来补偿可变增益模块和直流漂移校正模块在高频处的增益下降,从而达到拓展带宽、提高增益的效果。该可变增益放大器采用0.13mm SiGe BiCMOS工艺。测试结果表明,该款放大器3 dB带宽达到7.5 GHz,可变增益范围为40 dB (-10 dB-30 dB)。在10 Gb/s伪随机测试码输入的情况下,测试输出信号峰峰抖动小于30 ps_pp,功耗为50 mW。由于无电感设计,该芯片的面积仅为0.53*0.27 mm₂。     

A wideband RF amplifier for satellite tuners

This paper presents the design and measured performance of a wideband amplifier for a direct conversion satellite tuner.It is composed of a wideband low noise amplifier(LNA) and a two-stage RF variable gain amplifier(VGA) with linear gain in dB and temperature compensation schemes.To meet the system linearity requirement, an improved distortion compensation technique and a bypass mode are applied on the LNA to deal with the large input signal.Wideband matching is achieved by resistive feedback and an off-chip LC-ladder matching network.A large gain control range(over 80 dB) is achieved by the VGA with process voltage and temperature compensation and dB linearization.In total,the amplifier consumes up to 26 mA current from a 3.3 V power supply. It is fabricated in a 0.35-μm SiGe BiCMOS technology and occupies a silicon area of 0.25 mm~2.     

一种应用于卫星电视调谐器的宽带射频放大器

本文给出了一种应用于直接变频结构的卫星电视调谐器接收机的射频放大器的设计和测试结果。射频放大器由一个宽带低噪声放大器和一个带增益补偿的两级可变增益放大器组成。为了满足系统对线性度的要求,低噪声放大器采用了一种失真抵消技术并增加了大信号输入旁路工作模式。射频放大器采用电阻负反馈和片外电容电感阶梯网络实现宽带匹配。可变增益放大器实现超过80dB的增益控制范围,并带有工艺、电压和温度补偿及增益线性化电路。射频放大器采用3.3V单电源供电,总共消耗26mA电流。芯片采用0.35μm锗硅双极CMOS工艺制成,硅片面积仅0.25mm²。     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB (-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.     

一种基于g_m/I_D方法设计的可变增益放大器

提出了一种基于gm/ID方法设计的可变增益放大器。设计基于SMIC90nmCMOS工艺模型,可变增益放大器由一个固定增益级、两个可变增益级和一个增益控制器构成。固定增益级对输入信号预放大,以增加VGA最大增益。VGA的增益可变性由两个受增益控制器控制的可变增益级实现。运用gm/ID的综合设计方法,优化了任意工作范围内,基于gm/ID和VGS关系的晶体管设计,实现了低电压低功耗。为得到较宽的增益范围,应用了一种新颖的伪幂指函数。利用Cadence中spectre工具仿真,结果表明,在1.2 V的工作电压下,具有76 dB的增益,控制电压范围超过0.8 V,带宽范围从34 MHz到183.6 MHz,功耗为0.82 mW。     

A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

A high-linearity PGA (Programmable Gain Amplifier) with DC offset calibration loop is proposed in this paper. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem. This PGA is fabricated in TSMC 0.13um CMOS technology. The measurements show that the receiver PGA （RXPGA）provides 64dB gain range with a step of 1dB, and the transmitter PGA（TXPGA） covers 16dB gain. The RXPGA consumes 18mA and the TXPGA consumes 7mA (I and Q path) under 3.3V supply. The bandwidth of the multi-stage PGA is higher than 20MHz. In addition, the DCOC (DC offset cancellation) circuit shows 10KHz of HPCF (high pass cutoff frequency) and the DCOC settling time is less than 0.45µs.     

A low-noise widely tunable Gm-C filter with frequency calibration

A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 μm CMOS process. It exhibits a wide programmable bandwidth from 322.5 kHz to 20 MHz. Measured results show that the filter has low input referred noise of 5.9 nV/√Hz and high out-of-band ⅡP3 of 16.2 dBm. It consumes 4.2 and 9.5 mW from a 1 V power supply at its lowest and highest cut-off frequencies respectively.     

一种应用于RFID标签的新型功率放大器设计

A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm² in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

应用于DRM/DAB系统的高转换增益及线性度优化的新结构混频器

This paper focuses on a new design of a down-conversion mixer for a low-IF wideband receiver.Based on the folded structure and differential multiple gated transistor(DMGTR) technique,a novel quadrature mixer with a high conversion gain,a moderate linearity,and a moderate NF is proposed.The mixer is designed and implemented in a 0.18-m CMOS process,and can operate in a frequency range from 150 kHz to 1.5 GHz.The circuit performance is confirmed by both simulation and measurement results.The measurement results exhibit a peak conversion gain of 13.35 dB,a high third order input referred intercept point of 14.85 dBm,and a moderate single side band noise figure of 10.67 dB.Moreover,the whole quadrature mixer core occupies a compact die area of 0.122 mm2.It consumes a current of 3.96 mA(excluding the output buffers) under a single supply voltage of 1.8 V.     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.