一种偏置电流可调节的高效率2.4GHz锗硅功率放大器

基于IBM0.35μm SiGe BiCMOS工艺BiCMOS5PAe实现了一种偏置电流可调节的高效率2.4GHz锗硅功率放大器。该功率放大器采用两级单端结构和一种新型偏置电路,除射频扼流电感外,其它元件均片内集成。采用的新型偏置电路用于调节功率放大器的静态偏置电流,使功率放大器工作在高功率模式状态或低功率模式状态。在3.5V电源条件下,功率放大器在低功率模式下工作时,与工作在高功率模式下相比,其功率附加效率在输出0dBm时提高了56.7%,在输出20dBm时提高了19.2%。芯片的尺寸为1.32mm×1.37mm。     

应用于TD-LTE的SiGe BiCMOS功率 放大器的设计

针对准第四代无线通信技术TD-LTE中2.570~2.620 GHz频段的应用,设计了一款基于IBM SiGe BiCMOS7WL工艺的射频功率放大器。该功率放大器工作于AB类,采用单端结构,由两级共发射极电路级联构成,带有基极镇流电阻,除两个谐振电感采用片外元件外,其他全部元件均片上集成,芯片面积为(1.004×0.736)mm2。测试结果表明,在3.3 V电源电压下,电路总消耗电流为109 mA,放大器的功率增益为16 dB,输出1 dB增益压缩点为15 dBm。该驱动放大器具有良好的输入匹配,工作稳定。     

Linearity Improvement of a Power Amplifier Using a Series LC Resonant Circuit

A radio frequency power amplifier microwave monolithic integrated circuit with a series LC resonant circuit as well as a bias control circuit for wide-band code division multiple access application is presented. The linearizer that consists of a series LC resonant circuit and base-emitter junction of a bias transistor operates as a diode rectifier circuit. A comparison between the circuits with and without the linearizer has been demonstrated. The power amplifier (PA) with the series LC resonant linearizer exhibits adjacent channel leakage ratio-1 (ACLR1) of -37.2 dBc at output power of 27 dBm, a 5.6 dB improvement compared to the circuit without the linearizer. The bias control circuit reduces consumed average dc current from 83 mA to 57 mA for efficiency improvement. The linearized PA exhibits 1-dB compression point (P₁dB) of 29.3 dBm, power-added efficiency of 45.7%, and power gain of 20.6 dB at low quiescent current of 37 mA with a 3.4 V single supply.     

A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications

This paper demonstrates a two-stage 1.95-GHz WCDMA handset RFIC power amplifier (PA) implemented in a 0.25-/spl mu/m SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and collector voltage, the average power efficiency of the two-stage PA is improved from 1.9% to 5.0%. The measured power gain is 18.5 dB. The gain variation with dynamic biasing is less than 1.8 dB. An off-chip memoryless digital predistortion linearizer is also adopted, satisfying the 3GPP wideband code division multiple access (WCDMA) linearity specification by a 10 dB improvement of adjacent channel power ratio (ACPR) at +26 dBm average channel output power.     

A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier

A monolithic SiGe BiCMOS envelope-tracking power amplifier (PA) is demonstrated for 802.11g OFDM applications at 2.4 GHz. The 4-mm² die includes a high-efficiency high-precision envelope amplifier and a two-stage SiGe HBT PA for RF amplification. Off-chip digital predistortion is employed to improve EVM performance. The two-stage amplifier exhibits 12-dB gain, <5% EVM, 20-dBm OFDM output power, and an overall efficiency (including the envelope amplifier) of 28%.     

A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

This paper describes circuit design and measurement results of our newly developed InGaP/GaAs-HBT MMIC power amplifier (PA) module which can operate with 2.4-V low reference and low supply voltages of its on-chip bias circuits. To achieve the low-reference voltage operation, the following two new circuit design techniques are incorporated into the power amplifier: 1) AC-coupled, divided power stage configuration with two different kinds of bias feeding (voltage and current drive and only current drive) and 2) successful implementation of a diode linearizer built in the power stage. Theses two techniques allow the PA to offer smooth output transfer characteristics over a wide temperature range. Measurement results done under the conditions of 900 MHz, a 3.5-V collector voltage for power stage, and 2.4-V reference and collector voltages for the bias circuits show that the PA module meets J-/W-CDMA power and distortion requirements sufficiently over a wide temperature range from -10degC to 90degC while keeping a low quiescent current of less than 65 mA. For J-CDMA modulation, the module can deliver a 27.5-dBm output power (P_out), a 40% PAE, and a -50-dBc ACPR, while a 28-dBm P_out, a 42% PAE, and a -42-dBc ACLR are achieved for W-CDMA modulation.     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

Silicon-germanium BiCMOS HBT technology for wireless power amplifier applications

This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1.     

一种2.4 GHz全集成SiGe BiCMOS功率放大器

针对2.4 GHz 802.11 b/g无线局域网(WLAN)的应用,该文设计了一种单片全集成的射频功率放大器(PA)。由于在自适应偏置电路中采用异质结晶体管(HBT)和电容构成的简单结构提高PA的线性度,因此不增加PA的直流功耗、插损和芯片面积。在基极偏置的DC通路中采用电阻负反馈实现温度稳定功能,有效避免热崩溃的同时不引起射频损耗。采用了GRACE 0.18mSiGe BiCMOS 工艺流片,芯片面积为1.56 mm2,实现了包括所有偏置电路和匹配电路的片上全集成。测试结果表明,在2.4-2.5 GHz工作频段,PA的小信号S21增益达23 dB,输入回波损耗S11小于-15 dB。PA的 1 dB 输出压缩点的线性输出功率为19.6 dBm,功率附加效率为20%,功率增益为22 dB。     

A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

Investigation into SiGe HBT class E/F PA efficiency at 2 GHz for VDD from 1 to 1.8 V

This letter presents a 2-GHz SiGe heterojunction bipolar transistor fully integrated class E/F power amplifier (PA) design operating at low supply voltage. A maximum measured power added efficiency (PAE) of 39% is achieved for a supply voltage of 1.8V. At 1V, a maximum PAE of 36% is measured. The PA was fabricated using an advanced 0.18-/spl mu/m BiCMOS process.     

An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications

A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias control circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The adaptive bias control circuit detects the input power level and supplies a low quiescent current of 16 mA at the low output power level and an increased current up to 90 mA according to the increased power level adaptively. The intelligent W-CDMA power amplifier using the adaptive bias circuit exhibits an improvement of average power usage efficiency of more than 1.93 times, and an adjacent channel leakage ratio by 4 dB at the output power of 28.3 dBm.     

下一代移动通信LTE中功率放大器芯片设计

基于0.18μm SiGe BiCMOS工艺,设计了一种应用于下一代移动通信3GPP LTE TDD2.6 GHz频段(Band38)的射频功率放大器(PA)芯片。射频功率放大器采用共发射极3级级联的全差分结构,提高了输出电压摆幅,减小了功率晶体管的集电极电流,且降低了寄生的键合线电感。在预放大级和中间放大级、功率级中分别设计了电阻偏置和有源偏置两种偏置电路以提高线性度性能,并通过MOS开关管实现功率控制功能。测试结果表明:在2.57～2.62 GHz工作频段内,正向增益S21大于30.5 dB,输入回波损耗S11和输出回波损耗S22分别均小于-13 dB,功率增益大于31 dB,输出1 dB压缩点功率达28.6 dBm,功率附加效率为18%。     

S波段雷达接收机前端低噪声放大器

采用0.35μm SiGe BiCMOS工艺设计了用于S波段雷达接收机前端电路的低噪声放大器。对于现代无线接收机来说,其动态范围和灵敏度很大程度上都取决于低噪声放大器的噪声性能和线性度。相对于CMOS工艺来说,SiGe BiCMOS工艺具有更高的截止频率、更好的噪声性能和更高的电流增益,非常适合微波集成电路的设计。该低噪声放大器采用三级放大器级联的结构以满足高达30dB的增益要求。在5V的电源电压下,满足绝对稳定条件,在3GHz-3.5GHz频段内,功率增益为34.5dB,噪声系数为1.5dB,输出1dB功率压缩点为11dBm。     

基于SiGe工艺的高增益射频功率放大器

基于0.13μm SiGe HBT工艺,设计应用于无线局域网(WLAN)802.11b/g频段范围内的高增益射频功率放大器.该功放工作在AB类,由三级放大电路级联构成,并带有温度补偿和线性化的偏置电路.仿真结果显示:功率增益高达30dB,1dB压缩点输出功率为24dBm,电路的S参数S11在1.5～4GHz大的频率范围内均小于-17dB,S21大于30dB,输出匹配S22小于-10dB,S12小于-90dB.最高效率可达42.7%,1dB压缩点效率为37%.     

0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。     

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.     

一种电调Doherty功率放大器

提出了一种全新的电调Doherty移动基站功率放大器。该Doherty放大器的载波放大器和峰值放大器的驱动功率分配比及输出合成相位实现了电可调,从而保证了Doherty功率放大器的最佳驱动功率分配比,以及最佳的输出合成相位,同时结合内部线性化技术以实现Doherty功率放大器的最优性能。为保证功率放大器性能的稳定,设计了一种用于Doherty功率放大器的恒静态偏置电路,在-25℃～+50℃的高低温实验中使放大器偏置电流的波动小于5%。功放的工作频率为870～890MHz,增益大于58dB。在CDMA2000信号测试下,输出功率为50.06dBm时,其ACLR(邻道泄漏功率比)小于-47.5dBc,整机效率达42.3%(含驱动级)。     

基于0.35µm SiGe BiCMOS工艺的2.4GHz功率放大器

本文报道了基于0.35µm SiGe BiCMOS工艺的2.4GHz功率放大器的设计。为了降低PCB上的寄生效应,提高电路稳定性和增益,设计了带台面的金属板使芯片通过台面接地而避免通过PCB过孔接地。另外,输出匹配网络中采用了低通匹配形式,提高了电路的线性度和功率输出能力。在2.4GHz,测得1dB压缩点输出功率为15.7dBm,线性增益为27.6dB,S11和S22分别低于-7dB和-15dB。