基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

基于混合结构的一种高性能90nm CMOS逐次逼近A/D转换器

实现了一种10位2.5MS/s逐次逼近A/D转换器。在电路设计上采用了R-C混合结构D/A转换、伪差分比较结构以及低功耗电平转换方式实现。为了实现好的匹配性能,在版图布局上分别采用电阻梯伪电阻包围对策以及电容阵列共中心对称布局方式进行布局。整个A/D转换器基于90nm CMOS工艺实现,在3.3V模拟电源电压以及1.0V数字电源电压下,测得的DNL和INL分别为0.36LSB和0.69LSB。在采样频率为2.5MS/s,输入频率为1.2MHz时,测得的SFDR和ENOB分别为72.86dB和9.43bits。包括输出驱动在内,测得整个转换器的功耗为6.62mW。整个转换器的面积约为238um×214um。设计结果显示该转换器性能良好,非常适合多电源嵌入式SoC的应用。     

一种用于触摸屏SoC的10位200kS/s SAR ADC IP核

采用“5MSBs (Most-Significant-Bits) + 5LSBs (Least-Significant-Bits)”C-R混合式D/A转换方式以及低失调伪差分比较技术,结合电容阵列对称布局以及电阻梯低失配版图设计方法,基于0.18µm 1P5M CMOS Logic工艺,设计实现了一种用于触摸屏SoC (System-on-Chip)的8通道10位200kS/s逐次逼近型A/D转换器IP核。在1.8V电源电压下,测得的微分非线性误差和积分非线性误差分别为0.32LSB和0.81LSB。在采样频率为200kS/s,输入频率为91kHz时,测得的无杂散动态范围(SFDR: Spurious-Free Dynamic Range)和有效位数(ENOB: Effective-Number-of-Bits)分别为63.2dB和9.15bits,功耗仅为136µW。整个A/D转换器IP核的面积约为0.08mm2。设计结果显示该转换器满足触摸屏SoC的应用要求。     

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

Based on a 5 MSBs(most-significant-bits)-plus-5 LSBs(least-significant-bits) C-R hybrid D/A conversion and low-offset pseudo-differential comparison approach,with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method,an 8-channel 10-bit 200-kS/s SAR ADC(successive-approximation -register analog-to-digital converter) IP core for a touch screen SoC(system-on-chip) is implemented in a 0.18μm 1P5M CMOS logic process.Design considerations for the touch sc...     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm 3.3V标准数字工艺实现.     

200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm3.3V标准数字工艺实现     

一个10位、50MS/s CMOS折叠流水结构A/D转换器

在 0.6μmDPDM标准数字CMOS工艺条件下 ,实现 10位折叠流水结构A/D转换器 ,使用动态匹配技术 ,消除折叠预放电路的失调效应 ;提出基于单向隔离模拟开关的分步预处理 ,有效压缩了电路规模 ,降低了系统功耗 .在5V电源电压下 ,仿真结果为 :当采样频率为50MSPS时 ,功耗为 12 0mW ,输入模拟信号和二进制输出码之间延迟为2.5个时钟周期 ,芯片面积 1.44mm2 .     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

一种低功耗11位100MS/s采样率SAR ADC IP

本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗,flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性,在版图设计中,采用底板包围顶板的MOM电容结构,有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺,双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供电电压下消耗的总电流为2.92mA。在2.4MHz输入和50MHz输入下的有效转换位数（ENOB）分别为9.9位和9.34位。计算得出本设计的FOM值为18.3fJ/conversion-step。     

一种低功耗10位流水线结构的CMOS A/D转换器的设计

本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2.     

An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25 mm2

This article is presented to describe an area-efficient CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application, which is fully compatible with standard digital CMOS technology. A modified MOS-transistor-only folding block contributes to a small chip area. At the input stage, offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio (SNDR). An INL/DNL of 0.77 LSB/0.6 LSB was measured. An SNDR figure of 43.7 dB is achieved at 4 MHz input frequencies when operated at full speed of 200 MHz. The chip is realized in a standard digital 0.18 μm CMOS technology and consumes a total power of 181 mW from 3.3 V power supply. The active area is 0.25 mm².     

一种10位200 kS/s 65 nm CMOS SAR ADC IP核

该文基于65 nm CMOS低漏电工艺,设计了一种用于触摸屏SoC的8通道10位200 kS/s逐次逼近寄存器型(Successive Approximation Register,SAR) A/D转换器(Analog-to-Digital Converter,ADC) IP核。在D/A转换电路的设计上,采用7MSB (Most-Significant-Bit) + 3LSB (Least-Significant-Bit) R-C混合D/A转换方式,有效减小了IP核的面积,并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上,通过采用一种低失调伪差分比较技术,有效降低了输入失调电压。在版图设计上,结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322m267m。在2.5 V模拟电压以及1.2 V数字电压下,当采样频率为200 kS/s,输入频率为1.03 kHz时,测得的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)和有效位数(Effective Number Of Bits,ENOB)分别为68.2 dB和9.27,功耗仅为440W,测试结果表明本文ADC IP核非常适合嵌入式系统的应用。     

A 13-bit, 8 MSample/s pipeline A/D converter

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm IP6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.     

一个13位8兆采样率流水线模数转换器

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.     

一种57.6mW,10位,50MS/s流水线操作CMOS A/D转换器

在1.8V,0.18μm CMOS工艺下,实现了10位,50MS/s流水线操作A/D转换器的设计和测试.通过优化采样电容和运算跨导放大器(OTA)电流,并采用动态比较器,从而降低功耗;采用复位结构的采样/保持和余量增益电路消除OTA失调电压的影响;优化OTA的次极点,保证其工作稳定.测试结果表明:ADC在整个量化范围内无失码,功耗为57.6mW,失调电压为0.8mV,微分非线性为-0.6～0.7LSB.对5.1MHz的输入信号量化,可获得44.9dB的信号与噪声及谐波失真比.电路面积为0.52mm2.     

一种低功耗多谐振荡式电压频率转换器设计

提出一种新型的低功耗多谐振荡式电压频率转换器电路的设计,采用0.18μm CMOS工艺制程,拥有较大的输入电压范围,根据CSMC 0.18μm工艺参数,在Spectre上仿真。结果表明,该电路在0~1.6 V的输入电压下输出0~2.0 MHz的频率信号,灵敏度1.25 MHz/V,输出频率相对误差小于6.8%,电路的最大功耗0.23 m W。得到预期的设计结果。     

应用于CMOS图像传感器中带有失调电压消除功能的电容比值非相关十位循环式模数转换器

A 10-bit ratio-independent switch-capacitor（SC） cyclic analog-to-digital converter（ADC） with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio（SNDR） of 53.6 dB and a DNL of C0：12/0：14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.     

A 10-bit 110 MHz SAR ADC with asynchronous trimming in 65-nm CMOS

A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented. In this paper, a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals. As a result, the linearity of the SAR ADC will increase with high linearity sampled signals. Farther more, a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology. Additionally, the proposed comparator provides a better performance with the decreasing of power supply. Moreover, a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50% register delay. Lastly, an asynchronous trimming method is provided to make the capacitive-DAC settle up completely instead of using the redundant cycle which would prolong the whole conversion period. This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm² and consumes 1.8 mW. The SAR ADC achieves SFDR > 68 dB and SNDR > 57 dB, resulting in the FOM of 28 fJ/conversion-step. From the test results, the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.