纳米硅二极管的独特性能

摘要:使用PECVD薄膜淀积技术制成的纳米硅薄膜(nc-Si∶H)具有优异的性能。把纳米硅薄膜淀积在异型的单晶硅衬底上,制成了nc-Si/c-Si异质结二极管。研制成的纳米硅二极管具有许多优于传统硅二极管的独特性能。     

纳米硅/晶体硅异质结电池的暗I-V特性和输运机制

采用HWCVD技术在P型CZ晶体硅衬底上制备了纳米硅／晶体硅异质结太阳电池,测量了晶体硅表面在不同氢处理时间下的异质结的暗I-V特性和相应的电池性能参数．室温下的正向暗I-V特性采用双二极管模型来拟合,可将0～1V的电压范围区分为4个区域：旁路电阻（0～0．15V）、非理想二极管2（0．15～0．3V）、理想二极管1（0．3～0．5V）和串联电阻（〉0．5V）．拟合结果表明,适当的氖处理时间（～30s）可有效降低非理想二极管的理想因子n2,即降低界面复合电流,表明具有好的界面特性．对于282～335K的暗I—V温度特性的研究表明,在0．15～0．3V的低电压范围,暗电流主要由耗尽区的复合电流提供,0．3～0．5V电压范围,对输运起主要作用的是隧穿过程,该过程可用通过界面陷阱能级的隧穿模型来解释．     

高效硅基异质结太阳能电池的模拟

a-Si:H/c-Si异质结太阳能电池的基本参数,如层厚度、掺杂浓度、a-Si:H/c-Si界面缺陷、功函数等是影响载流子传输特性和电池效率的关键因素。在本文中,利用AFORS-HET程序,研究了这些参数与a-Si:H/c-Si电池的性能的关联性。最后,具有TCO/n-a-Si:H/i-a-Si:H/p-c-Si/p -a-Si:H/Ag结构的太阳能电池的最优化性能被获得,其光电转换效率为27.07%（VOC: 749 mV, JSC: 42.86 mA/cm2, FF: 84.33%）。深入地了解异质结电池的输运特性,对进一步提高电池的效率有很大的帮助,同时对实际太阳能电池的制造也能提供有益的指导。     

扇形分裂漏CMOS磁敏传感器集成电路

介绍了扇形分裂漏磁敏传感器集成电路的设计,并由0．6μm CMOS工艺实现。该集成电路以扇形分裂漏磁敏MOS管作为磁敏传感单元,并包含两次工作模式的开关阵列预处理电路、相关二次取样电路(CDS)和数字控制电路。该传感器集成电路实现了测量磁场的功能,并实现了在屏蔽磁场的工作模式下对噪声信号进行校正的功能,有效地消除了磁敏传感器及其信号处理电路的噪声影响。在工作频率为10 kHz时,磁敏传感器的灵敏度为2．62 V/T。     

a-Si/c-Si异质结结构太阳能电池设计分析

通过应用 Scharfetter- Gum mel解法数值求解 Poisson方程 ,对热平衡态 a- Si/ c- Si异质结太阳能电池进行计算机数值模拟分析 ,着重阐述在 a- Si/ c- Si异质结太阳能电池中嵌入 i( a- Si:H)缓冲薄层的作用 ,指出采用嵌入 i( a- Si:H )缓冲薄层设计能有效增强光生载流子的传输与收集 ,从而提高 a- Si/ c- Si异质结太阳能电池的性能 ,同时还讨论 p+ ( a- Si:H)薄膜厚度和 p型掺杂浓度对光生载流子传输与收集的影响 ,而高强度光照射下模拟计算表明 ,a- Si/ c- Si异质结结构太阳能电池具有较高光稳定性     

基于InP-DHBT的20 GHz的超高速比较器

采用截止频率fT为170 GHz的InP-DHBT工艺,我们设计并制作了一个超高速主从电压比较器。整个芯片的面积（包括焊盘）是0.75?1.04 mm2,在-4V的单电源电压下消耗的功耗是440mW（不包括时钟产生部分）。整个芯片包含了77个InP DHBTs。比较器的尼奎斯特测试到了20GHz,输入灵敏度在10 GHz采样率的时候是6mV,在20 GHz的时候是16 mV。据我们所知,这在国内还是第一次在单片上集成超过70个InP DHBTs的电路,也是目前国内具有最高采样率的比较器。     

基于扇形霍尔板几何修正因子的分裂漏磁敏场效应晶体管相对灵敏度研究

采用保角变换方法推导出扇形霍尔板的几何修正因子,并根据几何修正因子得到扇形分裂漏场效应晶体管相对灵敏度的解析表达式.通过计算机模拟和实验测试结果的验证,进一步完善了扇形磁敏分裂漏场效应管相对灵敏度的数学模型.相比矩形结构磁敏场效应晶体管,扇形磁敏场效应晶体管具有更高的相对灵敏度.测试所获最大灵敏度为3.77%T-1,根据本文模型,最大相对灵敏度应为3.81%T-1.     

Effects of deposition pressure on the microstructural and optoelectrical properties of B-doped hydrogenated nanocrystalline silicon (nc-Si:H) thin films grown by hot-wire chemical vapor deposition

We report on the effects of deposition pressure P_d on the growth and properties of the B-doped nanocrystalline silicon (nc-Si:H) thin films grown by hot-wire chemical vapor deposition (HWCVD) at very high hydrogen dilution of 98.8%. We found that the crystallinity of nc-Si:H or μc-Si:H films is not only determined by hydrogen dilution but also the concentration ratio of atomic H to SiH₃ ([H]/[SiH₃]) on the growing surface which is varied with deposition pressure P_d. Furthermore, there is a threshold of [H]/[SiH₃] ratio which we name as overfull hydrogen (OH). When the [H]/[SiH₃] ratio is lower than the threshold OH ([H]/[SiH₃]<OH), the crystallinity of the nc-Si:H or μc-Si:H films increases with increasing [H]/[SiH₃] ratio. But when the [H]/[SiH₃] ratio is higher than the threshold OH ([H]/[SiH₃]>OH), the crystallinity decreases with increasing [H]/[SiH₃] ratio. Finally, the high conductivity of 4.22 S cm⁻¹ of the B-doped nc-Si:H thin film deposited at 15 Pa is obtained.     

11.6-GHz 1:4 regenerating demultiplexer with bit-rotation controland 6.1-GHz auto-latching phase-aligner ICs using AlGaAs/GaAs HBTtechnology

The authors present an 11.6-GHz 1:4 regenerating demultiplexer (demux) and a 6.1-GHz phase aligner, implemented using high-current-gain baseline AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology. The demux features a hybrid tree/shift register-type architecture optimized for high-speed and low-power operation, and is the fastest demux with bit-rotation control ever reported. It consumes 1.4 W of power with a single -5 V supply, and has a phase margin of 270° and differential input data sensitivity of 56 mV_p-p at 11.6 Gb/s. The phase aligner incorporates an auto-latching scheme which allows the data to be latched using a timing signal derived on-chip from the data, and is the fastest fully monolithic phase aligner ever reported. It dissipates 0.8 W of power with a single -5 V supply and has differential input data sensitivity of 60 mV_p-p at 6.1 Gb/s     

Characteristics of MSM photodetectors with trench electrodes onp-type Si wafer

U-grooved metal-semiconductor-metal photodetectors (UMSM-PD's) having various trench depths of interdigitated electrodes and an intrinsic hydrogenated amorphous silicon (i-a-Si:H) to c-Si heterojunction have been fabricated successfully on a p-type [100] Si wafer. The U-grooved structures on c-Si were achieved with a simple orientation-dependent etching (ODE) process. Some important characteristics of the obtained UMSM-PDs are presented and discussed. An UMSM-PD with a 70 nm i-a-Si:H overlayer, 1.45 μm-deep recessed electrodes, and 3 μm finger width and spacing, had a full width at half maximum (FWHM) of 50.6 ps and a full-time of 132 ps for its temporal response under a bias of 15 V. The significant improvements of transient response for UMSM-PD, as compared to the conventional one, were attributed to the trench electrodes resulted in a stronger lateral electric field in the light absorption region of photodetector. At a bias of 20 V, this UMSM-PD had a responsivity of 0.25 A/W as measured with an 0.83-μm incident semiconductor laser, a high photo/dark current ratio about 2000, and an internal quantum efficiency of 36%. This high photo/dark current ratio would be due to the additional i-a-Si:H overlayer on Si wafer. These mentioned performances were much better than those of the conventional Si-based planar MSM-PD     

Monolithic Photoreceiver Constructed With a ZnSe MSM Photodiode and an InGaP/GaAs HBT

The monolithic integration of a ZnSe metal–semiconductor–metal photodiode and an InGaP/GaAs heterojunction bipolar transistor has been achieved successfully on a GaAs substrate. As a result of a current amplification ratio of 20.8, the present monolithic photoreceiver illuminated at an optical input-power intensity of 10 $muhbox{W}$ has shown high voltage amplification sensitivity of $-hbox{29.6} hbox{mV}/muhbox{W}$. The fabrication process and characterization for the integrated device will be useful for the development of wide-bandgap-based short-wavelength optoelectronic integrated circuits in the future.      

Silicon heterojunction solar cell: a new buffer Layer concept with low-temperature epitaxial silicon

Amorphous silicon/crystalline silicon heterojunction solar cells, deposited by the plasma-enhanced chemical vapor deposition (PECVD) technique, have been fabricated using different technologies to passivate defects at the heterointerface: without treatment, the insertion of a thin intrinsic amorphous layer or that of a thin intrinsic epitaxial layer. The open circuit voltage of heterojunction solar cells fabricated including an intrinsic amorphous buffer layer is strangely lower than in devices with no buffer layer. The structure of the amorphous buffer layer is investigated by high resolution transmission electron microscope observations. As an alternative to amorphous silicon, the insertion of a fully epitaxial silicon layer, deposited at low temperature with conventional PECVD technique in a hydrogen-silane gas mixture, was tested. Using the amorphous silicon/crystalline silicon (p a-Si/i epi-Si/n c-Si) heterojunction structure in solar cells, a 13.5% efficiency and a 605-mV open circuit voltage were achieved on flat Czochralski silicon substrates. These results demonstrate that epitaxial silicon can be successfully used to passivate interface defects, allowing for an open circuit voltage gain of more than 50 mV compared to cells with no buffer layer. In this paper, the actual structure of the amorphous silicon buffer layer used in heterojunction solar cells is discussed. We make the hypothesis that this buffer layer, commonly considered amorphous, is actually epitaxial.     

A fully integrated 40-Gb/s clock and data recovery IC with 1:4DEMUX in SiGe technology

In this paper, a fully integrated 40-Gb/s clock and data recovery (CDR) IC with additional 1:4 demultiplexer (DEMUX) functionality is presented. The IC is implemented in a state-of-the-art production SiGe process. Its phase-locked-loop-based architecture with bang-bang-type phase detector (PD) provides maximum robustness. To the authors' best knowledge, it is the first 40-Gb/s CDR IC fabricated in a SiGe heterojunction bipolar technology (HBT). The measurement results demonstrate an input sensitivity of 42-mV single-ended data input swing at a bit-error rate (BER) of 10^-10. As demonstrated in optical transmission experiments with the IC embedded in a 40-Gb/s link, the CDR/DEMUX shows complete functionality as a single-chip-receiver IC. A BER of 10^-10 requires an optical signal-to-noise ratio of 23.3 dB     

Design of a CMOS oscillator with magnetic-field frequency modulation

A magnetosensitive n-channel split-drain MOSFET (MAGFET) integrated with a current-controlled oscillator on a single chip is described. This magnetically controlled oscillator (MCO), which was fabricated in 5-/spl mu/m CMOS technology, is sensitive to magnetic fields perpendicular to the chip surface. The output of the MCO is a square wave whose frequency varies linearly with, and is modulated by, the magnetic input signal.     

高电导本征纳米硅膜及其缓冲层太阳能电池

通过PECVD法制备了纳米硅薄膜(nc-Si:H),采用Raman散射谱,AFM对样品的结构和形貌进行了测试,并测试了样品的室温电导率。结果表明:制备出的纳米硅薄膜,其电导率达到4.9S·cm-1。另外制备了本征nc-Si:H膜作缓冲层,结构为ITO/n+-nc-Si:H/i-nc-Si:H/p-c-Si/Ag的PIN型太阳能电池,其Voc达到534.7mV,Isc达到49.24mA(3cm2),填充因子FF为0.4228。     

Monolithic SiGe HBT Feedforward Variable Gain Amplifiers for 5 GHz Applications

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled‐emitter resistor and the other using an HBT‐based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain‐control range of 23 dB with a control‐voltage range from 0.4 to 2.6 V. The gain‐tuning sensitivity is 90 mV/dB. At V_CTRL= 2.4 V, the 1 dB compression output power, P_1‐dB, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and ‐1.8 dBm and 71mA in a VGA with a constant current source, respectively.     

Research on ZnO/Si heterojunction solar cells

We put forward an n-ZnO/p-Si heterojunction solar cell model based on AFORS-HET simulations and provide experimental support in this article. ZnO:B (B-doped ZnO) thin films deposited by metal-organic chemical vapor deposition (MOCVD) are planned to act as electrical emitter layer on p-type c-Si substrate for photovoltaic applications. We investigate the effects of thickness, buffer layer, ZnO:B affinity and work function of electrodes on performances of solar cells through computer simulations using AFORS-HET software package. The energy conversion efficiency of the ZnO:B(n)/ZnO/c-Si(p) solar cell can achieve 17.16% (V_oc: 675.8 mV, J_sc:30.24 mA/cm², FF: 83.96%) via simulation. On a basis of optimized conditions in simulation, we carry out some experiments, which testify that the ZnO buffer layer of 20 nm contributes to improving performances of solar cells. The influences of growth temperature, thickness and diborane (B₂H₆) flow rates are also discussed. We achieve an appropriate condition for the fabrication of the solar cells using the MOCVD technique. The obtained conversion efficiency reaches 2.82% (V_oc: 294.4 mV, J_sc: 26.108 mA/cm², FF: 36.66%).     

A 165-Gb/s 4:1 Multiplexer in InP DHBT Technology

This paper presents a 4:1 multiplexer fabricated in InP double heterojunction bipolar transistor (DHBT) technology. The multiplexer works up to 165 Gb/s at a supply voltage of$-hbox3.2~V$consuming 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenge was to ensure correct timing between clock and data signals.     

A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

We present a pseudorandom bit sequence (PRBS) generator that outputs a 2⁷-1 bit pattern at rates up to 21 Gb/s. The circuit is implemented in a 40-GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) standard production process, operates from a single 3.3-V power supply, and consumes 1.1 W of power. We discuss variations of PRBS architecture and digital circuit topologies which exploit unique characteristics of AlGaAs/GaAs HBT devices. The work demonstrates the feasibility of using AlGaAs/GaAs HBT technology with low-voltage/low-power design techniques in complex high-speed circuits