低噪声CMOS运算放大器的优化设计方法

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.     

Ka频段低噪声放大器的设计

介绍了Ka频段低噪声放大器的设计方法，采用HP－EESOF公司Libra软件对有源器件进行直流分析与参数提取，并运用小信号线性分析法进行电路模拟与设计。研制的放大器在34－36GHz频率下噪声系数小于3dB。     

运算放大器的低频噪声测试方法

运算放大器广泛应用于电路设计中,其可靠性指标直接影响电路系统的性能.运放器件的低频噪声特征同其性能及可靠性指标密切相关.本文中详细给出了运放器件低频噪声的测试方法并对测试过程中的若干关键问题进行了深入剖析.     

5~6 GHz限幅低噪声放大器的研制

采用GaAs增强型pHEMT工艺,将限幅器和低噪声放大器集成在同一衬底,设计了一款用于5~6 GHz的限幅低噪声放大器。限幅器采用PIN二极管进行设计,低噪声放大器采用并联负反馈、源级电感负反馈以及电流复用结构,减小功耗的同时改善了增益平坦度和稳定性。测试结果表明,在工作频带内,限幅低噪声放大器的增益为27±0.2 dB,噪声系数为1.1~1.3 dB,总功耗为240 mW,耐功率大于46 dBm(2 ms脉宽,30%占空比),芯片尺寸为3.3 mm×1.3 mm。     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

CMOS运算放大器的设计与Cadence仿真

本文根据运算放大器的设计要求(开环电压增益、相位裕度),分析了CMOS运算放大器的性能参数,设计出器件的几何尺寸,最后通过Cadence仿真得到性能指标的仿真结果.     

GaAs cryo-cooled LNA for C-band radioastronomy applications

The design procedure and measurements of a C-band high-performance GaAs cryo-cooled low noise amplifier (LNA) are presented. The latter provides 30 dB gain, a noise figure (NF) lower than 0.12 dB (i.e. 8 K equivalent noise temperature) at 25 K operating temperature, with 35 mW DC bias power only. An appropriate scaling of the device gate periphery has been adopted to trade-off the LNA's NF and DC power consumption.     

一种兼顾速度和功率损耗的硅探测器模拟前端电路设计

提出了一种兼顾速度和功率损耗的增益可调模拟前端电路,适用于硅探测器。该电路主要由快速电荷灵敏放大器、整形器以及可调节主要参数的控制系统组成。其中快速电荷灵敏放大器由低噪音场效晶体管（JFET）和电流反馈运算放大器构成,以确保较高频率和较短上升时间。整形器为五阶复数滤波器,能够提供较高的对称脉冲。通过实验验证了其可行性,在电容小于100 pF的范围内,实现了6种可调增益且兼顾了速度和功率损耗,电荷灵敏放大器上升时间为12ns,功率损耗为96mW。当探测器电容为40 pF时,等效噪音电荷（ENC）均值为180e-。     

High-performance in W-band monolithic pseudomorphic InGaAsHEMT LNA's and design/analysis methodology

High-performance W-band monolithic one- and two-stage low noise amplifiers (LNAs) based on pseudomorphic InGaAs-GaAs HEMT devices have been developed. The one-stage amplifier has a measured noise figure of 5.1 dB with an associated gain of 7 dB from 92 to 95 GHz, and the two-stage amplifier has a measured small signal gain of 13.3 dB at 94 GHz and 17 dB at 89 GHz with a noise figure of 5.5 dB from 91 to 95 GHz. An eight-stage LNA built by cascading four of these monolithic two-stage LNA chips demonstrates 49 dB gain and 6.5 dB noise figure at 94 GHz. A rigorous analysis procedure was incorporated in the design, including accurate active device modeling and full-wave EM analysis of passive structures. The first pass success of these LNA chip designs indicates the importance of a rigorous design/analysis methodology in millimeter-wave monolithic IC development     

集成运算放大器同相和反相形式的E_n-I_n噪声分析和比较

本文通过分析和比较同相和反相放大器E_n-I_n噪声的特点,给出了若干新结果。本文方法在低噪声运放电路设计和运放噪声参数提取中都具有十分重要的意义。     

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

低频低噪声集成运放XD1531的设计和分析

本文阐明了低频低噪声运放XD1531的设计原理。从电路和版图设计两方面论述了该电路整个设计过程。针对电路第一级的结构,采用低频低噪声方法进行设计。在版图方面主要考虑了降低低频噪声,尤其是降低表面1/f噪声的措施。通过对XD1531噪声性能的分析以及与国内外同类产品的比较,说明了该集成电路具有低噪声特性。同时,说明本文提出的设计方法对于降低集成电路的低频噪声是有效的。     

瞬变光探测系统前置放大电路的设计

光电探测器前置放大电路设计的好坏会直接影响整个检测系统的信噪比.为了提高对微弱光信号的检测精度,使用低噪声光电二极管和运算放大器,并选择光电二极管工作在光伏模式,设计出了光电探测器的低噪声前置放大电路.通过采用超前校正方法对由光电二极管结电容及运算放大器输入电容引起的相移进行补偿,克服了光电二极管寄生参数引起的转换电路...     

轨到轨输入输出范围运算放大器的噪声分析和优化

这篇文章设计了一个轨到轨（Rail-to-Rail）输入输出范围的低噪声运算放大器,在输入级采用电流补偿的方法来稳定该运算放大器在整个输入共模范围内的跨导,在输出级使用了AB类的输出方法来提高运算放大器的输出范围,且详细分析了该运算放大器的噪声性能,在此基础上给出了改善该运算放大器噪声性能的方法,以此来提高该运算放大器的动态范围。     

Theoretical analysis of low phase noise design of CMOS VCO

A theoretical analysis on low phase noise of voltage-controlled oscillators (VCOs) based on complementary cross-coupled LC VCO by 0.35-/spl mu/m complementary metal oxide semiconductor technology is demonstrated. From the procedure of optimization steps, the excess noise factor of the amplifier coming from the active device has been determined. The proposed VCO operates at 2 GHz with phase noise of -116 dBc/Hz at offset frequency 600 kHz. The power consumption is 22.62 mW under 3 V bias with 9.1% frequency tuning. The achievement of low phase noise is also matched with prediction by formula in the frequency domain.     

双声道混合音频系统的设计与实现

基于运算放大器及功率放大器等集成电路,设计实现了两路声道输入及单声道输出的音频系统。论述了该系统的设计过程,并通过测试表明该系统具有声音响亮、噪声低、无失真等特点,取得了较好的音频性能,且具有广泛的应用前景及实用价值。     

NBTI机制下运算放大器的性能退化分析及其可靠性设计

随着CMOS器件尺寸的不断缩小,集成电路设计阶段的可靠性问题变得愈加重要,NBTI效应作为重要的可靠性问题之一得到了大量的研究,并从电路级对其提出了改进。采用等效电路模型表征NBTI退化对模拟电路的影响,研究了两级运算放大器在NBTI效应影响下电路参数的退化,分析并确定了影响传统两级运算放大器性能的关键器件。在此基础上,对传统运放结构进行改进,引入反馈,使-3dB带宽的退化量由27%降到了1%左右,从而减小NBTI退化对电路性能的影响。     

On the performance analysis and design of an integrated front-end PIN/HBT photoreceiver

A detailed study on the performance analysis and optimum design of an integrated front-end PIN/HBT photoreceiver for fiber-optic communication is presented. Receiver circuits with two different transimpedance amplifiers-a single-stage common emitter (CE) amplifier and a three-stage amplifier comprising a CE amplifier and two emitter followers (EFs), are analyzed assuming a standard load of 50 /spl Omega/. A technique to include the transit-time effect of a PIN photodetector on the overall receiver circuit analysis is introduced and discussed. Gain-bandwidth product (GB) and gain-bandwidth-sensitivity measure product (GBS) are obtained as functions of feedback resistance (R/sub F/) and various device parameters. Hence, some optimum designs are suggested using a photodetector of area 100 /spl mu/m/sup 2/ and with a feedback resistance of 500 /spl Omega/. The bandwidth plays a major role in determining the optimum designs for maximum GB and maximum GBS. A bandwidth >8 GHz has been obtained for the photoreceiver even with a single-stage CE amplifier. The optimum design for a receiver with a three-stage amplifier shows a bandwidth of 35 GHz which is suitable for receivers operating well beyond 40 Gb/s; however, in this case, the gain is reduced. The performance of different fixed square-emitter structures are investigated to choose the optimum designs corresponding to different gains. Very low power dissipation has been estimated for the optimized devices. The noise performance of the devices with optimum designs was calculated in terms of the minimum detectable optical power for a fixed bit-error rate of 10/sup -9/. The present design indicates that GB and noise performance can be improved by using an optimum device design.     

RF Class-E Power Amplifier Design Based on a Load Line-Equivalent Capacitance Method

In this research work, an alternative methodology to design radio frequency (RF) class-E amplifier is proposed and verified. The conventional design procedure starts with a switch idealization of the device and extraction of the output capacitance based on S parameter measurements. Since these ideal conditions lead to non-optimal values at microwave frequencies, an optimization procedure on these values, using a non-linear model of the device, has to be applied in order to obtain higher performance. Unlike this legacy procedure, the proposed method starts the design of the RF class E power amplifier with the non-linear model directly to determine a more representative value of the equivalent capacitance, and thereby considering all the non-ideal and non-linear features of the device.     

基于电源调制及有源滤波匹配的双向放大器芯片设计

射频双向放大器作为雷达接收通道的前端模块芯片,其性能的优劣直接影响通道的性能。传统的双向放大器芯片往往是基于射频开关的拓扑结构设计的,在噪声性能和反向隔离度方面都有所不足。文中设计基于电源调制的双向放大器芯片,具有全新的电路拓扑结构,射频信号不通过射频开关而直接进入低噪声放大器,可以优化芯片的噪声性能;同时,截止的器件可以提高芯片的反向隔离度。设计中如何提高低噪声放大器的增益和噪声性能,以及如何利用有源滤波匹配技术实现射频输入输出端口的合并和匹配是两大难点和创新点。文中基于L 波段的双向放大器设计及流片的测试结果显示,芯片有良好的性能,充分验证了理论分析的正确性。