超薄HfN界面层对HfO_2栅介质Ge pMOSFET电性能的改进

通过在高k介质和Ge表面引入一层超薄HfN界面层,实验制备了HfO2/HfON叠层栅介质Ge MOS器件。与没有界面层的样品相比,HfO2/HfON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和高有效迁移率。因此利用HfON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的high-k/Ge界面质量有着重要的意义。     

Gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices by suitable HfAlO/HfON thickness and sintering temperature

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfAlO/HfON stacks and sintering temperatures are investigated in this work. The suppression of gate leakage current and improvement of reliability properties can be achieved by either stacked gate dielectrics or a low sintering temperature. Especially, the qualities of the interface and high-k gate dielectric in Ge devices are significantly improved through a low sintering temperature. A 0.5 nm HfAlO/2.5 nm HfON gate stack and a sintering temperature at 350 °C are the suitable conditions to achieve low EOT, gate leakage, and good reliability for Ge MOS devices.     

Effect of Si capping layer on the interface quality and NBTI of high mobility channel Ge-on-Si pMOSFETs

The effects of a Si capping layer on the device characteristics and negative bias temperature instability (NBTI) reliability were investigated for Ge-on-Si pMOSFETs. A Ge pMOSFET with a Si cap shows a lower subthreshold slope (SS), higher transconductance (G_m) and enhanced drive current. In addition, lower threshold voltage shift and G_m,max degradation are observed during NBTI stress. The primary reason for these characteristics is attributed to the improved interface quality at the high-k dielectric/substrate interface. Charge pumping was used to verify the presence of lower density of states in Ge pMOSFETs with a Si cap.     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Growth and characterization of germanium and boron doped silicon epitaxial films

The epitaxial growth and characterization of in-situ germanium and boron (Ge/B) doped Si epitaxial films is described. As indicated by secondary ion mass spectroscopy and spreading resistance measurements, the total and electrically activated B concentrations are essentially identical and independent of Ge incorporation. The B and Ge concentrations are uniformly distributed in these Ge/B doped films. A slight enhancement of Hall mobility is obtained, possibly due to the stress relief induced by Ge counterdoping. Carrier conduction in these films is due to the activated B with an activation energy of 0.04 eV as revealed by conductivity versus temperature measurements. Ge atoms appear to be isoelectronic with Si atoms in these films. A slight degradation of minority carrier diffusion length is observed. Electrical characterization of PN diodes on these Ge/B doped films do not reveal any anomaly. SiO₂ on these Ge/B doped films has similar oxide fixed charge density, interface state density and dielectric breakdown strength compared to silicon dioxide on boron doped epitaxial films. Electron injection reveals a different transport mechanism of the SiO₂ grown on these Ge/B doped films.     

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO/sub 2/. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO/sub 2/ films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300/spl deg/C in crystallization temperature compared to HfO/sub 2/. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (/spl sim/14) is larger than that of HfO/sub 2/ (/spl sim/7.8). HfON dielectrics exhibit /spl sim/10/spl times/ lower leakage current (J) than HfO/sub 2/ for the same EOTs before post-metal anneal (PMA), while /spl sim/40/spl times/ lower J after PMA. The improved electrical properties of HfON over HfO/sub 2/ can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (/spl Delta/V) of HfON capacitor was found to be slightly larger than that of HfO/sub 2/. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm/sup 2//Vsec. By high temperature forming gas anneal at 600/spl deg/C, mobility improved up to 256 cm/sup 2//Vsec.     

UHV/CVD法生长硅基低位错密度厚锗外延层

采用超高真空化学气相淀积系统,以高纯Si2 H6和GeH4作为生长气源,用低温缓冲层技术在Si(001)衬底上成功生长出厚的纯Ge外延层.对Si衬底上外延的纯Ge层用反射式高能电子衍射仪、原子力显微镜、X射线双晶衍射曲线和Ra-man谱进行了表征.结果表明在Si基上生长的约550nm厚的Ge外延层,表面粗糙度小于1nm,XRD双晶衍射曲线和Ra-man谱Ge-Ge模半高宽分别为530'和5.5cm-1,具有良好的结晶质量.位错腐蚀结果显示线位错密度小于5×105cm-2可用于制备Si基长波长集成光电探测器和Si基高速电子器件.     

(Si/Ge)n多层薄膜的设计制备及光吸收性能

采用射频磁控溅射技术,在石英玻璃衬底上沉积了具有不同层数和厚度的(Si/Ge)n多层薄膜。XRD、Raman光谱测试表明,溅射态薄膜为微晶结构,在溅射过程中层间扩散形成Si-Ge振动键,溅射时间和薄膜层数影响着薄膜层间的扩散和结晶率;FESEM结果表明,薄膜表面由颗粒团簇构成,层与层之间有明显界面。UV-vis光谱测试表明,(Si/Ge)n多层薄膜在可见光范围内具有较宽的吸收,增加薄膜层数可扩大太阳能光谱的响应范围,而增加Si单层膜厚度对光吸收范围的影响较小。     

Si／Ge应变层异质结价带偏移的剪裁与设计

讨论应变层异质结价带偏移的剪裁、设计方法，研究Ｓｉ／Ｇｅ应变层异质结价带偏移设计参数与应变条件的关系，基于异质结中平均键能“对齐”，得到适用于Ｓｉ／Ｇｅ异质结价带偏移剪裁与设计的计算公式和图表。     

Interaction of self-assembled Ge islands and adjacent Si layers grown on unpatterned and patterned Si(001) substrates

For use in electronic devices, self-assembled Ge islands formed on Si(001) must be covered with an additional Si layer. Chemically vapor deposited Si layers initially grow very rapidly over Ge islands because of the catalytic effect of Ge on the reaction of the Si-containing gas. The edges of the Si features covering Ge “pyramids” are rotated by 45° with respect to the edges of the Ge pyramids because of the different mechanisms orienting the Ge islands and the Si features. When multiple layers of islands are formed, the in-plane ordering of the Ge islands depends on the thickness of the Si interlayer separating the island layers. When selective Si is grown on a patterned Si wafer to form the underlying structure for the Ge islands, the position of the islands is influenced by the detailed shape of the Si near the edges, which in turn depends on the thickness of the selectively deposited Si, the pattern size, and the amount of surrounding oxide.     

Si_(1-x)Ge_x薄膜Ge表面偏聚的Monte Carlo模型

目前已经有许多学者研究了用 UHV/CVD方法生长 Si1-x Gex 薄膜时 Ge在表面、次表面的偏聚。一种对这种实验结果的解释是由于化学原因 (例如氧化 )造成锗原子的化学势差 ,这种化学势差成为锗原子迁移产生锗偏聚的动力。本文通过应用一个简单的统计热力学模型 ,对在这种机理下产生的锗偏聚进行了研究。这种用 Monte Carlo方法建立的模型所得到的计算结果与实验结果相当吻合。     

Ge/Si量子点的控制生长

采用离子束溅射技术,在生长了Si缓冲层的硅晶片上制备了一系列Ge量子点样品.借助原子力显微镜(AFM)和Raman光谱等测试手段研究了Ge/Si量子点生长密度、尺寸及排列均匀性的演变规律.结果表明,改变Si缓冲层厚度及其生长方式,可以有效控制量子点的尺寸、均匀性和密度.随缓冲层厚度增大,量子点密度先增大后减小,停顿生长有利于提高缓冲层结晶性,从而提高量子点的密度,可以达到1.9×1010 cm-2.还研究了Si缓冲层在Ge量子点生长过程中的作用,并提出了量子点的生长模型.     

DCXRD分析Ge/Si(001)多层纳米岛材料

结合透射电镜与原子力显微镜实验,用双晶X射线衍射方法分析了Ge/Si多层纳米岛材料.衍射的卫星峰可以被分解为两个洛仑兹峰,它们分别源于材料的浸润层区和纳米岛区.利用透射电镜得到Si和SiGe层的厚度比,估算出浸润层区与岛区的Ge组分分别为0.51和0.67.这是一种简单估算Ge/Si多层纳米岛材料中Ge组分的方法.     

DCXRD分析Ge/Si(001)多层纳米岛材料

结合透射电镜与原子力显微镜实验,用双晶X射线衍射方法分析了Ge/Si多层纳米岛材料.衍射的卫星峰可以被分解为两个洛仑兹峰,它们分别源于材料的浸润层区和纳米岛区.利用透射电镜得到Si和SiGe层的厚度比,估算出浸润层区与岛区的Ge组分分别为0.51和0.67.这是一种简单估算Ge/Si多层纳米岛材料中Ge组分的方法.     

硅锗合金氧化后生成的锗纳米结构的特性研究

我们将SiGe合金在干氧吹气环境下以不同的温度和不同的时值进行氧化处理，用卢摄福散射仪RBS和高精度椭偏仪HP-ESM测量样品，获得10～80nm厚的硅氧化层和1nm厚的富锗层．新发现快速氧化生成的氧化膜表面有1～2nm厚的锗层．分析了锗纳米结构对应的PL发光谱，注意到锗纳米层对应的541nm波长的尖锐的发光峰和不同尺寸的锗原子团对应的从550～720nm波长的发光带．从量子受限模型和局域密度泛函计算出发。合理地解释了实验的结果．     

Research progress of Si-based germanium materials and devices

Si-based germanium is considered to be a promising platform for the integration of electronic and photonic devices due to its high carrier mobility, good optical properties, and compatibility with Si CMOS technology. However, some great challenges have to be confronted, such as: (1) the nature of indirect band gap of Ge; (2) the epitaxy of dislocation-free Ge layers on Si substrate; and (3) the immature technology for Ge devices. The aim of this paper is to give a review of the recent progress made in the field of epitaxy and optical properties of Ge heterostructures on Si substrate, as well as some key technologies on Ge devices. High crystal quality Ge epilayers, as well as Ge/SiGe multiple quantum wells with high Ge content, were successfully grown on Si substrate with a low-temperature Ge buffer layer. A local Ge condensation technique was proposed to prepare germanium-on-insulator (GOI) materials with high tensile strain for enhanced Ge direct band photoluminescence. The advances in formation of Ge n⁺p shallow junctions and the modulation of Schottky barrier height of metal/Ge contacts were a significant progress in Ge technology. Finally, the progress of Si-based Ge light emitters, photodetectors, and MOSFETs was briefly introduced. These results show that Si-based Ge heterostructure materials are promising for use in the next-generation of integrated circuits and optoelectronic circuits.     

复合量子阱Ge_(0.3)Si_(0.7)/(Ge_(0.3)Si_(0.7))_m-(Si)_m/Ge_(0.3)Si_(0.7)的电子能带结构

采用建立在经验赝历势基础上的推广k·P方法计算了复合量子阱Ge0.3Si0.7／（Ge0.3Si0.7）m-（Si）m／Ge0.3Si0.7的电子束缚能组及其活界面方向的色激关系,并与通常的单带模型下的包络函数方法的计算结果进行了比较。结果表明由于超晶格中子能带的形成,邻近能带间的互作用使通常单带模型下的包络函数方法不再能适用于复合量子阱的计算。计算结果也表明复合量子阱的电子束缚能级沿界面方向在kx＜0.1（2π/a）范围内基本上不随kx变化。     

Studies on the growth of CdTe on Si using ge interfacial layer in an organometallic vapor phase epitaxial system

Epitaxial CdTe layers were grown using organometallic vapor phase epitaxy on Si substrates with a Ge buffer layer. Ge layer was grown in the same reactor using germane gas and the reaction of germane gas with the native Si surface is studied in detail at low temperature. It is shown that germane gas can be used to “clean” the Si surface oxide prior to CdTe growth by first reducing the thin native oxide that may be present on Si. When Ge layer was grown on Si using germane gas, an induction period was observed before the continuous layer of Ge growth starts. This induction period is a function of the thickness of the native oxide present on Si and possible reasons for this behavior are outlined. Secondary ion mass spectrometry (SIMS) data show negligible outdiffusion and cross contamination of Ge in CdTe.     

不同界面层对HfTaON栅介质MOS特性的影响

采用磁控溅射方法,在Si衬底上制备HfTaON高k栅介质,研究了AlON、HfON、TaON不同界面层对MOS器件电特性的影响。结果表明,HfTaON/AlON叠层栅介质结构由于在AlON界面层附近形成一种Hf-Al-O"熵稳定"的亚稳态结构,且AlON具有较高的结晶温度、与Si接触有好的界面特性等,使制备的MOS器件表现出优良的电性能:低的界面态密度、低的栅极漏电、高的可靠性以及高的等效k值(21.2)。此外,N元素的加入可以抑制Hf和Ta的扩散,有效抑制界面态的产生,并使器件具有优良的抵抗高场应力的能力。     

Fully coherent Ge islands growth on Si nano-pillars by selective epitaxy

Our recent experimental results of Ge nanoheteroepitaxy (NHE) on Si nanopillars (NPs) are reviewed to confirm the possibility of relaxed Ge growth on Si without misfit dislocations (MDs) formation by elastic deformation. Selective Ge growth is performed by using reduced pressure chemical vapor deposition (CVD) on two types of Si NPs with thermal SiO₂ or CVD SiO₂ sidewalls and on Si nanoislands (NIs) on SiO₂. By using thermal SiO₂ sidewall, compressive strain is generated in the Si pillar and fixed by the thermal SiO₂. This results in an incoherent Ge growth on Si NPs due to MD formation. By using CVD SiO₂ sidewall, tensile strain formation due to thermal expansion during prebake for Ge epi process is observed. However, strain in Si due to Ge growth is not dominant. By introducing a Si_0.5Ge_0.5 buffer layer, no MD and stacking faults are observed by cross section TEM. The shape of Ge on Si NPs becomes more uniform due to improved crystal quality. On Si NIs on SiO₂, a clear compliance effect is observed after Ge growth. Coherent growth of Ge on Si is also realized on Si NIs by using Si_0.5Ge_0.5 buffer.