氮化硅扩散阻挡层在采用HfON栅介质的Ge MOS 电容中的作用

MOS capacitors with hafnium oxynitride（HfON）gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method.A large amount of fixed charges and interface traps exist at the Ge/HfON interface.HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing.A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier.Using this method,well behaved capacitance–voltage and current–voltage characteristics were obtained.Finally hystereses are compared under different process conditions and possible causes are discussed.     

Effect of ionizing radiation on MOS capacitors

A numerical model of metal-oxide-semiconductor (MOS) capacitor has been developed to investigate the effect of ionizing radiation on the characteristics of the device during exposure and also in the post-irradiated condition. The model takes into account the effect of radiation-induced changes in silicon-dioxide as well as in silicon substrate of MOS structure. It is found that the total high frequency capacitance of the device during exposure to radiation is different from its value in the post-irradiated condition. The results of the study are expected to be useful in predicting the behavior of MOS based devices operating in radiation environment.     

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO₂) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO₂ thicknesses, e.g., 2.5-10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO₂ thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO₂ high-k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.     

表面钝化对Ge MOS电容可靠性的影响

通过NO、N2O对Ge衬底进行表面钝化,然后采用反应磁控共溅射方法制备HfTiN薄膜,并利用湿N2气氛退火,将HfTiN转化为HfTiON高k栅介质.研究了表面钝化对Ge MOS器件性能的影响.实验结果表明,湿NO表面钝化能生长高质量GeOxNy界面层,有效降低MOS电容的栅极漏电流,增强器件的可靠性.     

Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric

Metal-oxide-semiconductor (MOS) devices, using a Si substrate and a thermal SiON film as the gate dielectric on a Ge layer, have been physically and electrically characterized. The small frequency dispersion and negligible hysteresis demonstrate very few oxide traps. The efficiency of Ge surface passivation is evidenced by the acceptable interface trap density of 7.08 × 10¹¹ cm⁻² eV⁻¹ close to midgap, which is critical for the enhancement of the carrier mobility in MOSFET devices. On the other hand, for the thermal SiON film, a higher permittivity of 4.86 can be achieved by NH₃ nitridation and a subsequent N₂O treatment of an as-grown SiO₂ film without compromising its leakage current. The conduction mechanism is confirmed to be Fowler-Nordheim (F-N) tunneling with extracted electron barrier height of 2.71 eV. Combining with these promising properties, the SiON film shows a great potential to further boost the performance of Ge MOSFETs. Most importantly, without using a Ge substrate, the SiON film on a Ge layer can be formed by the process fully compatible with incumbent ultra-large-scale integration (ULSI) technology, and hence, providing an economic way of fabricating high-performance Ge MOSFETs.     

Photoluminescence spectroscopy of sputtering Er-doped silicon-rich silicon nitride films

Er-doped silicon-rich silicon nitride (SRN) films were deposited on silicon substrate by an RF magnetron reaction sputtering system. After high temperature annealing, the films show intense photoluminescence in both the visible and infrared regions. Besides broad-band luminescence centered at 780 nm which originates from silicon nanocrystals, resolved peaks due to transitions from all high energy levels up to ~2H_(11/2) to the ground state of Er~(3+) are observed. Raman spectra and HRTEM measurements have been performed to investigate the structure of the films, and possible excitation processes are discussed.     

磁控溅射掺铒富硅氮化硅薄膜的光致荧光谱

Er-doped silicon-rich silicon nitride （SRN） films were deposited on silicon substrate by an RF magnetron reaction sputtering system. After high temperature annealing, the films show intense photoluminescence in both the visible and infrared regions. Besides broad-band luminescence centered at 780 nm which originates from silicon nanocrystals, resolved peaks due to transitions from all high energy levels up to 2H11/2 to the ground state of Er^3＋ are observed. Raman spectra and HRTEM measurements have been performed to investigate the structure of thefilms, and possible excitation processes are discussed.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

Limitations of conductance to the measurement of the interfacestate density of MOS capacitors with tunneling gate dielectrics

A systematic study of the uncertainties, sensitivity and limitations of the conductance technique for extracting the interface state density of tunneling dielectrics is presented. The methodology required to extract device parameters and interface state density from conductance and capacitance data is reviewed and analyzed. The effect of uncertainties in device parameters on extracted interface state density was determined using experimental results of thin oxides (1.4 nm and 2.0 nm). Modeling was used to indicate the effects of various device parameters on the sensitivity of conductance to changes in interface state density. The effect of uncertainties in insulator capacitance of equivalently thin dielectrics on uncertainties in extracted interface state density is minimal. The effect of uncertainties in series resistance increases with increasing bias towards accumulation. An increase in the series resistance of the device causes reduced sensitivity to changes in interface state density especially for interface states located nearer the majority band edge; increasing tunneling current causes increased uncertainties and reduced sensitivity to changes in interface state density especially for interface states nearer midgap     

氮化硅的ECCP刻蚀特性研究

本文对氮化硅的增强电容耦合等离子刻蚀进行研究,为氮化硅刻蚀工艺的优化提供参考。针对SF_6+O_2气体体系,通过设计实验考察了功率、压强、气体比、氦气等对刻蚀速率和均一性的影响,并对结果进行机理分析和讨论。实验结果表明:功率越大,刻蚀速率越大,与源极射频电力相比,偏置射频电力对刻蚀速率的影响更为显著;压强增大,刻蚀速率增大,但压强增大到一定程度后,刻蚀速率基本不变,刻蚀均匀性随着压强增大而变差;在保证SF_6/O_2总流量保持不变下,O_2的比例增大,刻蚀速率先增大后减小,刻蚀均匀性逐步变好;He的添加可以改善刻蚀均匀性,但He的添加量过多时,会造成刻蚀速率降低。     

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1E11 eV^-1cm^-2), gate leakage property (3.6E3 A/cm^2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.     

Effects of wet-ROA on shallow interface traps of n-type 4H-SiC MOS capacitors

The effects of wet re-oxidation annealing （wet-ROA） on the shallow interface traps of n-type 4H-SiC metal oxide-semiconductor （MOS） capacitors were investigated by Gray-Brown method and angle-dependent X- ray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps （Dit） from 0 to 0.2 eV below SiC conduction band edge （Ec） of the sample with wet-ROA for the first time, and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species, which results in C release and SiOxCy transformation into higher oxidation states, thus reducing the SiOxCy content and the SiOxCy interface transition region thickness.     

Study of ultrathin vanadium nitride as diffusion barrier for copper interconnect

Ultrathin Vanadium nitride (VN) thin film with thickness around 10 nm was studied as diffusion barrier between copper and SiO₂ or Si substrate. The VN film was prepared by reactive ion beam sputtering. X-ray diffraction, Auger electron spectroscopy, scanning electron microscopy and current-voltage (I-V) technique were applied to characterize the diffusion barrier properties for VN in Cu/VN/Si and Cu/VN/SiO₂ structures. The as-deposited VN film was amorphous and could be thermal stable up to 800 °C annealing. Multiple results show that the ultrathin VN film has good diffusion barrier properties for copper.     

Processing and characterisation of PECVD silicon nitride films

Amorphous Si-N films are synthesised from an NH₃/SiH₄ gas mixture by plasma-enhanced chemical vapour deposition (PECVD) at fixed radio frequency (13.56 MHz) and total gas pressure (34 ± 4 Torr). The variable process parameters and their ranges are: (i) substrate temperature, 200–400°C; (ii) RF power density, 0.08–0.35 W cm⁻²; (iii) NH₃/SiH₄ flow ratio, 40:400–40: 1200 ml min⁻¹. Fundamental properties of the Si-N films are characterised through elemental composition, chemical speciation, optical and electrical properties, all of which are dependent on the process parameters.     

基于夹层氮化硅波导的可见-中红外超连续谱特性研究

提出一种低厚度氮化硅-蓝宝石-氮化硅夹层波导结构。利用其色散波辐射现象和中红外相位匹配条件,结合波导脉冲传输模型,讨论了夹层波导不同物理尺寸对相位匹配点和光谱展宽的影响,数值模拟获得了0.5~4 μm的超连续谱展宽,并且在-40 dB水平下具有更远中红外色散波产生。通过该模型,详细解释了非线性波导脉冲传输的潜在机制。理论模型分析表明,通过优化氮化硅及蓝宝石夹层的物理尺寸,进而改变相位匹配条件,可以在较宽的波长范围内控制色散波的位置。     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

表面钝化对HfTiON栅介质Ge MOS电容性能的影响

通过NO、N2O对Ge衬底进行表面钝化,生长GeOxNy界面层,然后采用反应磁控共溅射方法制备HfTiN薄膜,并利用湿N2气氛退火,将HfTiN转化为HfTiON高κ栅介质.研究了表面钝化对MOS器件性能的影响,结果表明,湿NO表面钝化能改善界面质量,有效降低MOS电容的栅极漏电流,增强器件的可靠性.     

MOS capacitors obtained by wet oxidation of n-type 4H-SiC pre-implanted with nitrogen

The manufacture process and the electrical characterization of MOS devices fabricated by wet oxidation of N⁺ implanted n-type 4H-SiC are here presented. Different implantation fluence and energy values were used with the aims to study the effect of the N concentration both at the SiO₂/SiC interface and within the SiO₂ film. High doses, able to amorphise a surface SiC layer to take advantage of the faster oxidation rate of amorphous with respect to crystalline SiC, were also evaluated. The electrical quality of the SiO₂/SiC system was characterized by capacitance-voltage measurements of MOS capacitors. The analyses of the collected data show that only the implanted N which is located at the oxide-SiC interfaces is effective to reduce the interface states density. On the contrary, the interface states density remains high (the same of an un-implanted reference sample) when the implanted N is completely embedded in the region consumed by the oxidation. Furthermore, none generation of fixed positive charges in the oxide was found as a consequence of the different N concentrations enclosed in the oxide films. These results were independent of the amorphisation of the implanted layer by the N⁺ ions. Our results demonstrate that by using a suitable N ion implantation and an appropriate wet oxidation treatment, it is possible to obtain a reduced thermal budget process able to decrease the interface state density near the conduction band edge. The proposed approach should be interesting for the development of the MOSFET technology on SiC.     

Effect of Si nanoparticles on electronic transport mechanisms in P-doped silicon-rich silicon nitride/c-Si heterojunction devices

We successfully fabricated hetero-junction (H-J) devices from P-doped silicon-rich SiN_x embedded with Si nanoparticles on a p-type crystalline Si substrate at low temperature. High-resolution transmission electron microscopy (HRTEM) analysis indicates that the thin films contain nano-crystallites. The H-J devices showed a good rectification ratio at room temperature. Three distinct regions of temperature dependent J-V characteristics curve can be identified, where different current density variations are indicated. In the low voltage range, the current across the interface of H-J follows an ohmic behavior. In the intermediate range of voltage, the current transport mechanism shows a transition from the phosphorus diffusion to tunneling dominant due to the silicon nanoparticle size and interface of HJ device changed, while the space-charge-limited current (SCLC) dominates the conduction mechanism in the high voltage range and the density of trapping states also affects the electron transport proceeding. At last, the proper size of silicon nanoparticle can reduces the interface charge density of H-J, which is confirmed via the numerical C-V matching technique and we propose a new energy band diagram to fit the HJ device embedded by the silicon nanoparticles.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。