一种基于标准CMOS工艺的光互连方案探讨

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P＋/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance： with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.     

一种基于标准CMOS工艺的单片光互连

探索了采用标准CMOS工艺实现单片光互连的可行性。采用特许(Chartered)半导体公司3.3V、0.35μm标准模拟CMOS工艺设计并制造了一种单片光互连系统,并用两种结构研究了衬底噪声耦合对互连性能的影响。测试结果表明:该光互连系统可工作于几×103Hz,验证了基于标准CMOS工艺的单片光互连系统是可行的。     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10~(-9). The chip dissipates 60 mW under a single 3.3 V supply.     

基于标准CMOS工艺的1.5Gb/s单片集成光接收机

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.     

低损耗聚合物互连光波导的制备及性能测试

对应用于宽带光互连的光印刷电路板(OPCB)制备技术进行了研究。作为光互连系统的传输介质,我们研究了互连光波导的性能。基于紫外光刻技术,在常规PCB基底上制备了聚合物光波导,研究了光波导的制备流程以及工艺参数;并且通过不断优化工艺参数,制备得到了低损耗的光波导;通过测试光波导的传输损耗以及眼图,分析了光波导的性能。光波导在850nm波长条件下的传输损耗可以达到0.13dB/cm,实现了10Gbit/s光通信信号的传输。     

A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.     

一种集成MSM光电探测器的单片标准CMOS全差分光接收机

This paper presents a realization of a silicon-based standard CMOS,fully differential optoelectronic integrated receiver based on a metal–semiconductor–metal light detector（MSM photodetector）.In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents.The optoelectronic integrated receiver was designed and implemented in a chartered 0.35μm, 3.3 V standard CMOS process.For 850 nm wavelength,it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetector’s low capacitance and high intrinsic bandwidth.In addition,it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to–3 dB frequency.     

标准CMOS工艺下高速集成大光敏面光电探测器芯片的研制

为提高大纤芯(1mm)塑料(POF)光纤通信用的 单片集成光接收机(OEIC)的速率并降低成 本,对Si基大光敏面光电探测器(PD)的结构、性能以及后续放大电路进行了研究。首先 ,基于标准CMOS 工艺流程对N⁺/N-well/ p-sub PD结构进行建模和优化设计,对其光谱响应曲线和频率 特性曲线进行了仿真; 其次,建立PD等效电路模型,结合设计的后续放大电路进行协同设计与仿真;最后,采用0.5μm CMOS工 艺对单个面积为200μm×200μm的PD以及后续放大电路单片集成电路进行了流片、 封装和测试。实验结 果表明,在－2.5V偏压下和650nm波长入射 光,N⁺/N-well/p-sub PD的响应度约有0.12A/W,暗电流约为－9pA;单 片光接收机在小于10－9的误码率BER条件下,灵敏度为－23dBm,并得到250Mbit/s速率的清晰眼图。     

一种基于标准CMOS工艺的新型单片集成紫外图像传感器

我们提出了一种基于标准CMOS工艺的浮栅紫外图像传感器。传感器单元是由一个非常紧凑的紫外线灵敏器件构成。整个紫外图像传感器有一CMOS像素单元阵列、高压开关、读出电路和数字控制等部分组成。在一0.18μm标准工艺上实现了1个1616的图像传感器芯片。我们对传感器单元和阵列进行了测试,测试结果表明传感器的灵敏度为0.072 V/(mJ/cm2),并且可以获得紫外图像。此紫外图像传感器适合于大规模集成的生物医药和太空探测等领域。     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

基于标准CMOS工艺线性APD倍增区的优化仿真

采用标准CMOS工艺制备的n~+-p-π-p~+结构的线性APD,其倍增区p层的掺杂分布极大地影响着器件的性能.采用Silvaco仿真软件对倍增区p层进行了设计仿真,研究了p层的注入剂量和注入峰值浓度深度对器件特性的影响.仿真结果表明,设定器件增益为50,在p层的最佳注入剂量为1.82×10~(12)/cm~2,峰值浓度深度为2.1μm左右的最佳工艺条件下,器件的工作电压为73.1 V,过剩噪声因子为4.59,过剩噪声指数在0.34~0.45之间(波长λ=800 nm),优于目前已报道的结果.通过工艺的优化,器件的性能可以得到进一步提高.     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

A toroidal inductor integrated in a standard CMOS process

This paper presents a toroidal inductor integrated in a standard 0.13 μm CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches are followed and the results are compared; this comparison provides useful guidelines for the design of the device. A very simple Π model for low frequencies is derived from 1-port and 2-port measurements, and a good matching with general theory is observed. The coil exhibits an inductance between 0.9 nH and 1.1 nH up to 20 GHz (physical limit for the measurement equipment) and a quality factor approaching 10 at 15 GHz. No self-resonance is observed within the measurement range.     

Substrate noise isolation improvement in a single-well standard CMOS process

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.     

基于65 nm标准CMOS工艺的3.0 THz 探测器

基于Dyakonov和Shur等离子体波振荡原理设计并流片制备了一种采用65 nm标准CMOS工艺的3.0THz探测器,探测器包括贴片天线、NMOS场效应晶体管、匹配网络及陷波滤波器。探测器在室温条件下可达到526 V/W的响应率(Rv)和73 pW/Hz1/2的噪声等效功率(NEP)。采用该探测器和步进电机搭建了太赫兹扫描成像系统,获得了太赫兹源出射光斑的远场形状,光斑的半高宽(FWHM)为240μm;并对聚甲醛牙签和树叶进行了扫描成像实验,结果表明CMOS太赫兹探测器在成像领域有潜在的应用前景。     

RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications

In this paper a radio frequency (RF) to direct current (DC) voltage converter with multi-stage rectifiers is reported for micro power conversion in RF power harvesting systems. The purpose of this paper is to select an appropriate structure for the micro power-converters, operating in high frequencies. The main idea is to convert RF range sinusoidal signals to a DC voltage to produce power for the rest of the electrical circuit or a system. The reported rectifier demonstrated an efficiency of 10% at large span of frequency for input signal of 350 mV. In the presented work, an analytical and numerical study of the micro power-converters is reported for various applications. Different design parameters have been investigated for an efficient structure design including, number of MOSs, DC current of a known load, size of MOSFETs capacitors, and frequency of the operation. Consequently, optimized parameters have been reported in order to improve the RF to DC conversion efficiency. Reported circuits were designed and simulated in 180 nm twin-well CMOS process with low threshold metal-oxide semiconductor field-effect transistors (MOSFETS); this multistage rectifier occupied an area of 0.23 mm × 0.146 mm and it produced an output voltage of 2 V at its output. This output voltage can provide the supply voltage required to operate the RFID processing circuitry. Post layout simulations demonstrated that for thirteen stages of the rectifiers, the efficiency of 10% for a capacitive load of 10 pF has been achieved.     

一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...