脉冲激光模拟单粒子锁定试验研究

This paper introduces major characteristics of the single event latchup（SEL） in CMOS devices.We accomplish SEL tests for CPU and SRAM devices through the simulation by a pulse laser.The laser simulation results give the energy threshold for samples to undergo SEL.SEL current pulses are measured for CMOS devices in the latchup state,the sensitive areas in the devices are acquired,the major traits,causing large scale circuits to undergo SEL,are summarized,and the test equivalence between a pulse laser and ions is also analyzed.     

基于MEDICI的CMOS反相器SEL特性分析

文章利用计算机模拟的方法分析了不同衬底CMOS反相器的单粒子闩锁（SEL）特性,分别对不同衬底CMOS反相器在电极分布和输出不同的情况下进行了研究,首先在不同电极分布时．通过电闩锁对器件进行模拟．得出不同电极分布时器件的维持电压,然后进行SEL模拟．根据模拟结果,我们发现在维持电压最小的电极分布情况下,粒子入射到阱-衬底结时,输出低电平时,器件产生闩锁后N衬底器件比P衬底器件闩锁电流大．输出高电平时．器件产生闩锁后P村底器件比N衬底器件的闩锁电流大。通过对不同衬底器件SEL阈值的测试,我们得到N村底器件比P衬底器件对SEL敏感．器件输出高电平时比输出低电平对SEL略敏感。     

DSP处理器单粒子翻转率测试系统的研制

航天器及其内部元器件在太空中会受到单粒子效应(SEE)带来的威胁,因此航天用电子器件在装备前必须进行抗SEE能力的测试评估。针对传统测试方法存在的测试系统程序容易在辐照过程崩溃、统计翻转数不准确、单粒子闩锁(SEL)辨别不清晰和忽略内核翻转统计等问题,设计了一种测试系统,通过片外加载与运行程序从而减少因辐照导致片内程序异常的现象;通过片外主控电路统计被测电路翻转数使统计翻转结果准确;通过主控电路控制被测电路时钟供给排除因频率增加导致电流过大而误判发生SEL的情况;通过内核指令集统计内核翻转数。实验结果表明,该测试系统可以实时全面地监测数字信号处理器(DSP)的SEE,并有效防止辐照实验器件(DUT)因SEL而失效。     

Fault-tolerant TMR and DMR circuits with latchup protection switches

The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.     

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n⁺-p⁺ spacing L longer than 8 μm, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 μm     

输出对CMOS反相器SEL特性的影响评估

文中通过计算机模拟的方法分析了器件在不同输出电平时,CMOS反相器单粒子闩锁（SEL）特性的变化。通过对器件输出电平不同时,不同衬底的CMOS反相器进行仿真研究,我们得出,P衬底器件输出为高电平时比输出为低电平时得到的闩锁电流大,而N衬底器件在输出不同时,得到的闩锁电流大小相近。对于同种衬底的器件在输出不同时对SEL的敏感性几乎相同。在深亚微米的器件中,输出对器件SEL特性的影响均较大,需要在研究器件SEL特性时把其考虑在内。     

深亚微米CMOS反相器的单粒子瞬态效应研究

针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值范围。同时,开展脉冲激光模拟单粒子瞬态效应试验,定位该器件单粒子瞬态效应的敏感区域,捕捉不同辐照能量下器件产生的单粒子瞬态脉冲,确定单粒子瞬态效应的阈值范围,并与仿真结果进行对比分析。     

Latchup suppression in fine-dimension shallow p-well CMOS circuits

The high packing density required for VLSI CMOS circuits leads to enhanced performance of the inherent parasitic bipolar devices, and thus latchup becomes a major problem. One of the most attractive techniques for overcoming this is to fabricate the devices on n-on-n⁺epitaxial substrate material. This paper deals with latchup suppression by such a technique in fine-dimension CMOS circuits based on very shallow p-wells. Experimental results demonstrate that latchup may be eliminated in structures with p-well depths as shallow as 0.8 µm at supply voltages up to 10 V and temperatures up to 140°C. Furthermore, this may be achieved with no significant degradation of other aspects of device or circuit performance. A simple lumped model equivalent circuit has been used to predict latchup characteristics where appropriate, and in general this gives good agreement with experiment.     

Static and transient latchup simulation of VLSI-CMOS with an improved physical design model

We are presenting an improved latchup design model for static and transient latchup simulation of VLSI CMOS devices. The model is based on a decomposition of the CMOS structure into a network of analytically described current elements for both majority and minority carriers. Average doping densities and geometrical parameters are the physically based input data. For the modeling of the 2-D majority-carrier flow, transmission-line elements are introduced, especially in the inhomogeneously doped transition region between the substrate and an epitaxial layer. For modeling the transient current behavior, diffusion and space-charge capacitances are used. The model yields very good agreement with measurements both for static and transient triggering modes. Due to the physically reasonable assumptions used in the model equations, the influence of design variations on latchup characteristics can be predicted adequately without new parameter fitting.     

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

CMOS latchup and electrostatic discharge (ESD) continue to be a semiconductor quality and reliability area of interest as semiconductor components continue to be reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, CMOS latchup and ESD robustness will continue to be a technology concern. With both the revolutionary and evolutionary changes in CMOS and Silicon Germanium semiconductor technologies, and changing product environments, new CMOS latchup and ESD requirements also continue in semiconductor design, device and chip-level simulation, design verification, chip-to-system evaluation, and the need for new latchup and ESD test specifications. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of latchup and ESD. Although latchup and ESD are not a new reliability arena, there are also new issues rising each year, making the latchup and ESD an area of continuous discovery, innovation and invention. In this paper, an introduction to latchup in CMOS and BiCMOS Silicon Germanium will be discussed.     

A VLSI-suitable Schottky-barrier CMOS process

Trenched Schottky-barrier (TSB) contact PMOS devices for use in latchup-free CMOS are examined in detail, and compared to Schottky-contact PMOS. Measurements and simulations show that the TSB structure has significant advantages in gain and current leakage over the Schottky-contact structure. CMOS using TSB PMOS may be made unconditionally free of latchup. The tradeoffs involving PMOS source-drain implant dose are made explicit and correlated to latchup measurements.     

Infrared microscopy study of anomalous latchup characteristics dueto current redistribution in different parasitic paths

Anomalous effects such as abrupt variations of the latchup current in steady-state conditions and window effects, i.e. the existence of a well-defined interval of I/O injected currents for latchup to occur, can occur during pulsed latchup tests. Infrared microscopy allows the correlation of electrical characteristics with latchup current distribution and reveals that anomalous effects are due to the dynamic competition between different latchup paths. This is confirmed by a SPICE simulation of the lumped equivalent circuit of a CMOS output comprising two coupled p-n-p-n parasitic structures     

1/4-µm CMOS isolation technique using selective epitaxy

A new CMOS isolation technique has been developed for reducing isolation width to a 1/4 µm with large latchup immunity. This technique is supported by three key processes. The first is to form 1/4 µm thick insulator films on trench sidewalls, which are shaped perpendicularly to the substrate surface plane. The second is to refill the trenches with selectively grown single-crystal silicon with a planar surface. The third is to form a low-resistance well for latchup prevention. The CMOS devices are composed of n-channel devices fabricated on a p-type substrate and p-channel devices fabricated on an n-type epi-layer. In this isolation structure, a parasitic MIS operation with vertical channel induces large leakage currents along the isolation sidewalls. However, the highly doped p-type region, due to deep boron implant in the p-type substrate, is effective to suppress parasitic operation. Submicrometer-gate CMOS inverter operation is shown, when the channel stop implant is carried out.     

Temperature dependence of latchup in CMOS circuits

Measurements of the temperature dependence of holding current in bulk CMOS devices indicate that a substantial improvement in latchup resistance may be achieved by liquid-nitrogen temperature operation of CMOS technology.     

65 nm体硅工艺NMOS中单粒子多瞬态效应的研究

针对NMOS场效应晶体管由重离子辐射诱导发生的单粒子多瞬态现象,参考65 nm体硅CMOS的单粒子瞬态效应的试验数据,采用TCAD仿真手段,搭建了65 nm体硅NMOS晶体管的TCAD模型,并进一步对无加固结构、保护环结构、保护漏结构以及保护环加保护漏结构的抗单粒子瞬态效应的机理和能力进行仿真分析。结果表明,NMOS器件的源结和保护环结构的抗单粒子多瞬态效应的效果更加明显。     

A new approach to model CMOS latchup

Based upon the concept of the λ-typeI-Vcharacteristics, CMOS latchup is modeled and latchup criteria are constructed. According to the model and the criteria, conditions which lead to latchup can be expressed in terms of triggering currents, parasitic resistances, and device parameters. Therefore, latchup initiation can be predicted. Both transient simulation results and experimental results coincide with theoretical predictions and calculations. This substantiates the correctness of the proposed model.     

Analysis of latchup-induced photon emissions

Latchup-induced photon emission from CMOS devices is studied and compared with photon emission from hot carriers. Experiments revealed fundamental differences in spectral characteristics. By exploiting these differences, latchup sites are identified and depicted in high resolution. An effective method of separating photon emission patterns by passing through bandpass optical filters is described. It is shown that the photon emission mechanism from latchup is phonon-assisted electron-hole recombination     

A comprehensive geometrical and biasing analysis for latchup in 0.18-μm CoSi2 STI CMOS structure

This paper evaluates the effects of dimension variations on the latchup immunity of 0.18-μm CoSi₂ shallow trench isolation (STI) CMOS structures. A comprehensive study on the test devices, by variations of geometrical dimensions as well as the spacings, has been established. Focus has also been given to the dimensions of the STI structure, mainly on the width and depth, as the rest of the parameters are varied. The influence of biasing condition on latchup has also been investigated. The results obtained and the as-developed characterization techniques shall bestow a CMOS device that promises optimized layout dimension.     

CMOS闩锁效应模型分析及计算机模拟

本文采用较全面的包括四个寄生双极晶体管和MOS管的闩锁模型,详细分析了瞬态辐照下CMOS反相器的闩锁效应。通过模型分析探讨,得出了电路发生闩锁的内在条件,并和惯用的简化模型发生闩锁的内在条件进行了对比讨论。利用LSTRAC-2电路分析程序对本模型和惯用简化模型进行了模拟,就模拟结果和理论分析结果进行了分析比较。