一种新型的带栅形条电容和可变间距电容的惯性信号检测结构

The comb capacitances fabricated by deep reactive ion etching （RIE） process have high aspect ratio which is usually smaller than 30 ： 1 for the complicated process factors, and the combs are usually not parallel due to the well-known micro-loading effect and other process factors, which restricts the increase of the seismic mass by increasing the thickness of comb to reduce the thermal mechanical noise and the decrease of the gap of the comb capacitances for increasing the sensitive capacitance to reduce the electrical noise. Aiming at the disadvantage of the deep RIE, a novel capacitive micro-accelerometer with grid strip capacitances and sensing gap alterable capacitances is developed. One part of sensing of inertial signal of the micro-accelerometer is by the grid strip capacitances whose overlapping area is variable and which do not have the non-parallel plate＇s effect caused by the deep RIE process. Another part is by the sensing gap alterable capacitances whose gap between combs can be reduced by the actuators. The designed initial gap of the alterable comb capacitances is relatively large to depress the effect of the maximum aspect ratio （30 ： 1） of deep RIE process. The initial gap of the capacitance of the actuator is smaller than the one of the comb capacitances. The difference between the two gaps is the initial gap of the sensitive capacitor. The designed structure depresses greatly the requirement of deep RIE process. The effects of non-parallel combs on the accelerometer are also analyzed. The characteristics of the micro-accelerometer are discussed by field emission microscopy （FEM） tool ANSYS. The tested devices based on slide-film damping effect are fabricated, and the tested quality factor is 514, which shows that grid strip capacitance design can partly improve the resolution and also prove the feasibility of the designed silicon-glass anodically bonding process.     

倾斜梳齿的MEMS电容式传感器惯性脉冲响应特性研究

 DRIE(Deep Reactive Ion Etching)工艺加工的高深宽比梳齿电容不能保证绝对平行.本文在考虑低真空空气阻尼力的同时,研究了梳齿电容倾斜的MEMS传感器对脉冲惯性信号的响应,并分析了DRIE工艺因素对器件性能的影响.研究结果表明,当传感器为没有静电力反馈的双边电容结构时,梳齿电容的不平行对传感器的响应位移、惯性脉冲响应线性度范围影响明显,且随着封装真空度增加而加重.若传感器有静电力反馈,惯性脉冲响应的灵敏度降低,但DRIE工艺因素的影响程度降低.为了抑制DRIE工艺导致的梳齿电容不平行因素的影响,文中还设计了一个新型的变电容面积的MEMS惯性传感器,并用ANSYS初步分析了其性能,设计了其详细的制作工艺流程.     

新型磁驱动增大检测电容的高精度MEMS惯性传感器研究

增大传感器振子的质量和静态测试电容可以减小电容式MEMS惯性传感系统的噪声,而深度粒子反应刻蚀工艺由于复杂的工艺原因,当深宽比较大时,不能刻蚀出大质量和大初始电容的传感器.据此,本文研究了一种磁驱动增大检测电容的MEMS惯性传感器,通过电磁驱动器,传感器的静态测试电容可以大幅增加,在梳齿电容上刻蚀阻尼槽后,其机械噪声达到0.61μg每根号赫兹,仿真其共振频率为598Hz,静态位移灵敏度为0.7μm每重力加速度,基于硅 玻璃键合工艺,制作了栅形条电容式惯性传感器,并用电磁驱动的方式测试其品质因子达到715,从而验证了制作工艺的可行性和电磁驱动器改变传感器初始静态测试电容的可行性.     

Characteristics of a novel biaxial capacitive MEMS accelerometer

A novel MEMS accelerometer with grid strip capacitors is developed.The mechanical and electrical noise can be reduced greatly for the novel structure design.ANSOFT-Maxwell software was used to analyze the fringing electric field of the grid strip structure and its effects on the designed accelerometer.The effects of the width,thickness and overlapping width of the grid strip on the sensing capacitance are analyzed by using the ANSOFT-Maxwell software.The results show that the parameters have little effect on the characteristics of the presented accelerometer.The designed accelerometer was fabricated based on deep RIE and silicon-glass bonding processes.The preliminary tested sensitivities are 0.53 pF/g and 0.49 pF/g in the x and y axis directions,respectively.A resonator with grid strip structure was also fabricated whose tested quality factor is 514 in air,which proves that the grid strip structure can reduce mechanical noise.     

A novel MEMS inertial sensor with enhanced sensing capacitors

A novel MEMS inertial sensor with enhanced sensing capacitors is developed. The designed fabricated process of the sensor is a deep RIE process, which can increase the mass of the seismic to reduce the mechanical noise, and the designed capacitance sensing method is changing the capacitance area, which can reduce the air damping between the sensing capacitor plates and reduce the requirement for the DRIE process precision, and reduce the electronic noise by increasing the sensing voltage to improve the resolution. The design and simulation are also verified by using the FEM tool ANSYS. The simulated results show that the transverse sensitivity of the sensor is approximately equal to zero. Finally, the fabricated process based on silicon-glass bonding and the preliminary test results of the device for testing grid capacitors and the novel inertial sensor are presented. The testing quality factor of the testing device based on the slide-film damping effect is 514, which shows that the enhanced capacitors can reduce mechanical noise. The preliminary testing result of the sensitivity is 0.492 pf/g.     

一个新型的大检测电容结构的MEMS惯性传感器研究

A novel MEMS inertial sensor with enhanced sensing capacitors is developed. The designed fabricated process of the sensor is a deep RIE process, which can increase the mass of the seismic to reduce the mechanical noise, and the designed capacitance sensing method is changing the capacitance area, which can reduce the air damping between the sensing capacitor plates and reduce the requirement for the DRIE process precision, and reduce the electronic noise by increasing the sensing voltage to improve the resolution. The design and simulation are also verified by using the FEM tool ANSYS. The simulated results show that the transverse sensitivity of the sensor is approximately equal to zero. Finally, the fabricated process based on silicon-glass bonding and the preliminary test results of the device for testing grid capacitors and the novel inertial sensor are presented. The testing quality factor of the testing device based on the slide-film damping effect is 514, which shows that the enhanced capacitors can reduce mechanical noise. The preliminary testing result of the sensitivity is 0.492pf/g.     

一种新型的基于滑膜阻尼的电容式双向MEMS惯性传感器

设计了一个新型的结构完全对称的双向MEMS电容式惯性传感器.该传感器主要由可动质量块、栅形条、支撑梁、连接梁、阻尼调整梳齿组成.设计的结构采用变电容面积的检测方式,在降低空气阻尼的同时也降低了对DRIE工艺的要求,并通过加大测试信号电压来降低电路噪声,从而提高传感器的分辨率.用有限元工具ANSYS详细讨论了传感器的参数和性能,并模拟验证了设计的双向传感器的交叉效应近似为零.制作了滑膜阻尼测试器件,在大气压下,测得的品质因子可达514,验证了该结构设计可以提高传感器的分辨率和该工艺设计的可行性.     

一种新型的基于滑膜阻尼的电容式双向MEMS惯性传感器

设计了一个新型的结构完全对称的双向MEMS电容式惯性传感器.该传感器主要由可动质量块、栅形条、支撑梁、连接梁、阻尼调整梳齿组成.设计的结构采用变电容面积的检测方式,在降低空气阻尼的同时也降低了对DRIE工艺的要求,并通过加大测试信号电压来降低电路噪声,从而提高传感器的分辨率.用有限元工具ANSYS详细讨论了传感器的参数和性能,并模拟验证了设计的双向传感器的交叉效应近似为零.制作了滑膜阻尼测试器件,在大气压下,测得的品质因子可达514,验证了该结构设计可以提高传感器的分辨率和该工艺设计的可行性.     

Measurement method for accurate extraction of the base-to-emitterintrinsic and peripheral capacitances of bipolar transistors

A simple measurement method to determine the intrinsic and peripheral emitter junction capacitances is described. The method is based on measurements of BJT's with different emitter geometries and is demonstrated on transistors of an advanced BiCMOS technology. The method can be applied directly to standard deep-submicrometer devices. No special test devices are required. By determining peripheral capacitance for different processes, the method enables the examination of process schemes designed to suppress the effect of the peripheral emitter on the transistor action. The method also provides a useful approach to monitor the scaling behavior of the intrinsic and peripheral capacitances. Results indicate the peripheral capacitance starts dominating the total capacitance as the emitter is scaled into the submicrometer range. For devices with quarter micron emitter widths, the peripheral capacitance is found to be 3 to 4 times higher than the intrinsic capacitance, and puts a fundamental limitation on device design     

新型双向电容式MEMS加速度计特性分析

文章研究了一新型的栅形条电容MEMS加速度计,通过新型结构设计降低了传感器的机械噪声和电子噪声。用软件ANSOFT-Maxwell对栅形条电容的宽度、厚度及叠加宽度对检测电容的影响进行了分析。用深度离子刻蚀工艺和硅-玻璃键合工艺制作了传感器,初步测试结果表明其在X和Y方向的灵敏度分别为0.53pF/g 、0.49pF/g。制作的栅形条谐振子在大气下的品质因子达到514,说明栅形条结构可大大降低机械噪声。     

高深宽比深隔离槽的刻蚀技术研究

体硅集成MEMS器件中的一个非常重要的技术就是微结构与电路部分的电隔离和互连。由于体硅工艺与传统CMOS工艺不兼容 ,所以形成高深宽比的深隔离槽 (宽约 3μm ,深 2 0～ 10 0μm)是体硅集成中急待解决的工艺难题。本文采用MEMS微加工的DRIE (DeepReactiveIonEtching)技术、热氧化技术和多晶硅填充技术 ,形成了高深宽比的深电隔离槽 (宽 3.6 μm ,深 85μm)。还提出了一种改变深槽形状的方法 ,使深槽的开口变大 ,以利于多晶硅的填充 ,避免了空洞的产生     

一种高分辨率电容微加速度计的设计研究

分析了影响加速度计分辨率的因素,在此基础上,通过采用深度反应离子刻蚀工艺获得大的敏感质量和小的电极间隙、采用电容变化量比枝齿梳状敏感结构大一倍的直齿梳状敏感结构和利用静电负刚度来降低结构的刚度等措施提高器件分辨率。最后给出了一种新的设计方案,叙述了其工作原理并分析了影响其闭环灵敏度的因素。     

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

Influence of illumination on MIS capacitances in the strong inversion region

A simple analysis is presented of the effect of illumination on MIS capacitance in the strong inversion region. The two mechanisms responsible for the increase of capacitance under illumination are described: the decrease of the time constant generation of the inversion layer, and the decrease of the space-charge region under illumination. The theoretical results are compared with the experimental data on silicon and tellurium MIS capacitances.     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

一种谐振式微加速度计的设计

提出一种基于谐振原理、电容检测的微型加速度计。通过外加加速度使质量块经杠杆将力放大施加到谐振器上,改变谐振梁上的轴向应力,从而改变谐振梁的振动频率。研究表明这种加速度计的测量范围达66 g。同时采用有限元法进行了仿真模拟,结果显示传感器灵敏度约18 Hz/g,工作模态固有频率为625.981 kHz。     

A novel method to characterize parasitic capacitances in MOSFET's

A new technique exploiting the body effect is presented to separate intrinsic from extrinsic capacitances in submicron MOSFET's. The method has been validated using 2D numerical simulations and results obtained with transistors fabricated with 0.7 μm CMOS technology are presented     

High Aspect Ratio Vertical Cantilever RF-MEMS Variable Capacitor

An electrostatically actuated, microwave microelectromechanical system variable capacitor fabricated using deep X-ray lithography is presented. A single exposure has been used to produce the novel high aspect ratio microstructure, which includes a thin, vertically oriented, movable nickel cantilever beam and a 40:1 vertical aspect ratio capacitance gap. The 0.8-pF capacitor operates in the 1-5GHz region and has Q-factors of 36 at 4GHz and 133 at 2 GHz. The variable capacitance ratio is 1.24:1 over a 20-V tuning range at 4GHz     

Accurate metallization capacitances for integrated circuits and packages

The parallel-plate formula is widely used by the solid-state circuit designer to estimate capacitances in integrated circuits. Since considerable errors may result from using this approximation, this correspondence gives correction curves for a wide range of parameters. It is shown that the finite conductor thickness may significantly contribute to the increase in capacitance.     

Calculation of distributed capacitances of spiral resonators

A method for calculating the distributed capacitances and resonant frequencies of spiral resonators is described. First, the charge distribution on a spiral is found by a simplified model and the moment method, then the distributed capacitance is calculated. The equivalent inductance of the spiral resonator is then evaluated according to a standard formula, and the resonant frequencies are finally computed. The calculated results are compared with experimental data, and a good agreement between them is shown