Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.     

Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

An ultra-wideband (3.1-10.6 GHz) low-noise amplifier using the 0.18 μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm2.     

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system(GPS)receiver chip using 0.18 μm CMOS technology.Dual-conversion with a low-IF architecture was used for this GPS receiver.The receiver is composed of low noise amplifier(LNA),down-conversion mixers,band pass filter,received signal strength indicator,variable gain amplifier,programmable gain amplifier,ADC,PLL frequency synthesizer and other key blocks.The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB.The variable gain amplifier(VGA)and programmable gain amplifier(PGA)provide gain control dynamic range over 50 dB.The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2chip area including the ESD I/O pads.     

A millimeter wave linear superposition oscillator in 0.18 μm CMOS technology

This paper presents a millimeter wave （mm-wave） oscillator that generates signal at 36.56 GHz. The ram-wave oscillator is realized in a UMC 0.18 μm CMOS process. The linear superposition （LS） technique breaks through the limit of cut-off frequency （JET）, and realizes a much higher oscillation than Jr. Measurement results show that the LS oscillator produces a calibrated 37.17 dBm output power when biased at 1.8 V; the output power of fundamental signal is -10.85 dBm after calibration. The measured phase noise at 1 MHz frequency offset is -112.54 dBc/Hz at the frequency of 9.14 GHz. This circuit can be properly applied to mm-wave communication systems with advantages of low cost and high integration density.     

Design of a 0.18 μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier (LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91 × 0.53 mm2 while the total die area with ESD is 2.45 × 2.36 mm2.     

Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented.The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver.The area and power are decreased greatly compared with other designs.The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video.The 0.18μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC,which occupies a 2.6×2.6 mm~2 area and consumes 83 mW under typical work modes.     

Method of simulation of low dose rate for total dose effect in 0.18 μm CMOS technology

Three methods for simulating low dose rate irradiation are presented and experimentally verified by using 0.18 μm CMOS transistors.The results show that it is the best way to use a series of high dose rate irradiations, with 100 °C annealing steps in-between irradiation steps, to simulate a continuous low dose rate irradiation.This approach can reduce the low dose rate testing time by as much as a factor of 45 with respect to the actual 0.5 rad（Si）/s dose rate irradiation.The procedure also provides detailed information on the behavior of the test devices in a low dose rate environment.     

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process

An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.     

High LO-RF isolation of zero-IF mixer in 0.18 μm CMOS technology

In this study, we introduce a zero-IF sub-harmonic mixer with high isolation in the 5 GHz band using 0.18 μm CMOS technology. Placing an LC-Tank between the class AB stage and the mixer core improves the isolation between the LO to RF at low supply voltage. The measured isolation is 48 dB between the LO and RF ports, and the 9.5 dB conversion gain is achieved with a supply voltage of 7 mA at 2.5 V. In order to alleviate the degradation of linearity due to the high conversion gain, we adopt the class AB stage as RF input stage. The measured IIP₃ is −7.5 dBm. This work was supported by National Science Council of Taiwan, ROC under contract no. NSC94-2220-E-005-002.     

0.18 μm CMOS射频低噪声放大器设计

基于TSMC 0.18μm RFCMOS工艺,设计了一种工作于2.4 GHz频段的低噪声放大器。电路采用Cascode结构,为整个电路提供较高的增益,然后进行了阻抗匹配和噪声系数的性能分析,最后利用ADS2009对其进行了模拟优化。最后仿真结果显示。该放大器的正向功率增益为14 d B,噪声系数小于2 d B,1 d B压缩点为-13 d Bm,功耗为7.8 m W,具有良好的综合性能指标。     

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier(TIA),which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 m CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency(RF) ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency(IF) bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure(NF) is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.     

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity(10Ω·cm) silicon substrate is presented.The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization.The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane.The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance.The simulated S11 is less than –10 dB over 46–95 GHz,which is well matched with the measured results over the available 40–67 GHz frequency range from our measurement equipment.A maximum gain of –5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansoft HFSS simulation.Compared with the current state-of-the-art devices,the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.     

基于0.18 μm CMOS工艺8 bit/150 MHz折叠插值ADC

折叠插值模数转换器的转换速度快,可实现并行一步转换,但由于受到面积、功耗以及CMOS工艺线性度和增益的限制,其精度较低.提出了一种电流模均衡电路,能够有效地消除折叠电路中的共模影响,提高折叠电路增益及线性度,从而提高电路的转换精度.应用此技术,设计了一款折叠插值A/D转换器,工作电压为3.3 V,采样时钟为150 MHz,并通过0.18μm CMOS工艺实现,版图总面积为0.22 mm2.     

基于0.18µm CMOS工艺的高阶单环∑△ADC以及降采样数字滤波器的设计

设计了一个过采样、高阶一位单环∑△模数转换器以及后级降采样数字滤波器。整个芯片采用TSMC 0.18µm CMOS工艺实现,芯片面积1mm×2mm,功耗为56mW。 调制器采用1.8V全差分电路结构,在过采样率64,时钟频率81.92MHz,640kHz带宽内,实测精度达到了15.32位,动态范围94dB。降采样数字滤波器的通带波纹小于0.01dB,阻带衰减75dB,过渡带为640kHz-740kHz。     

A 1.2-V, 84-dB Σ△ ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.     

Rotary traveling-wave oscillator design using 0.18 μm CMOS

A rotary traveling-wave oscillator (RTWO) targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18 μm CMOS technology. Both simulation and measurement results are presented. The chip size including pads is 1.5 × 1.5 mm2. The measured output power at a frequency of 5.285 GHz is 6.68 dBm, with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

4-Bit Parallel-Input Exponential Digital-to-Analog Converter in CMOS 0.18 μm Technology

In this paper, a new digitally controlled linear-in-dB CMOS variable gain amplifier is proposed. The circuit employs the proposed novel approach in achieving a wide-range true-exponential transfer function e ^2X using a traditional pseudo-exponential amplifier followed by a variable gain stage, to expand the output dynamic range. A single digitally controlled variable resistor is used to tune the circuit accordingly by controlling X with a digital word. The result is a digitally controlled data conversion that yields a new type of non-linear digital-to-analog converter. Finally, a 4-bit converter is implemented in a TSMC 0.18 μm CMOS technology and displays a gain from about −21 dB to 36 dB in steps of 3.89 dB with an output linear error in [−0.66,0.45] dB and a static power consumption of 2.34 mW.     

Design of photovoltaic device and DC–DC converter on a single chip using 0.18 μm standard CMOS technology

In this paper, we propose a photovoltaic power supply for a stand-alone system that provides electrical generation and voltage boost functions on a single silicon chip. This power supply consists of solar cells, an oscillator, and a bootstrap charge pump, which are all designed in a 0.18 μm standard complementary metal-oxide semiconductor technology. Two types of solar cells are embedded in the system to improve its power efficiency. One type is used for the power supply and the other type is used to provide the voltage bias. Three different solar cells structures were designed. A pn structure and an np structure are used for the power supply cells and an npn series-connected structure is used for the oscillator circuit to operate the DC–DC converter The voltage-current characteristics of the solar cell under microscopic illumination have been measured and the performance of bootstrap charge pump circuits was confirmed. We remodeled our solar cell equivalent circuit to reflect these measurement results.     

Design of a 0.18μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier(LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage....