一种高性能宽带直接变频射频前端设计

提出一种宽带(250 MHz~4.7 GHz)无电感BiCMOS射频前端结构,包含低噪声跨导放大器(LNTA)、带电阻无源混频器和跨阻级。低噪声跨导放大器使用了噪声和线性度消除技术,例如输入交叉耦合结构、互补输入和电流复用技术。带电阻无源混频器采用退化电阻来提高线性度。仿真结果表明, 当电源电压为3.3 V时,总电流为9.38 mA, 噪声系数为9.8 dB(SSB),电压转换增益为20 dB,输入3阶交调为+11.8 dBm。     

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机.这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps.基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路.该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片.所测的接收机性能如下:噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV.该接收机采用1.8V电源电压,I,Q两路消耗的总电流为44mA.     

A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

This paper presents a wireless receiver front-end intended for cellular applications implemented in a 65 nm CMOS technology. The circuit features a low noise amplifier (LNA), quadrature passive mixers, and a frequency divider generating 25 % duty cycle quadrature local oscillator (LO) signals. A complementary common-gate LNA is used, and to meet the stringent linearity requirements it employs positive feedback with transistors biased in the sub-threshold region, resulting in cancellation of the third order non-linearity. The mixers are also linearized, using a baseband to LO bootstrap circuit. Measurements of the front-end show about 3.5 dB improvement in out-of-band IIP3 at optimum bias of the positive feedback devices in the LNA, resulting in an out-of-band IIP3 of 10 dBm. With a frequency range from 0.7 to 3 GHz the receiver front-end covers most important cellular bands, with an input return loss above 9 dB and a voltage gain exceeding 16 dB for all bias settings. The circuit consumes 4.38 mA from a 1.5 V supply.     

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...     

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2.4GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0.35μm CMOS工艺技术,在2V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3mA,输入三阶截距点达到20dBm,输出的信号幅度为87mV;下混频器消耗的电流为3.5mA,得到的转换增益是20dB,输入参考噪声电压是6.5nV/ Hz,输入三阶截距点为4.4dBm.     

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.     

RF front-end of direct conversion receiver RFIC for cdma-2000

We report on the front-end of a highly integrated dual-band direct-conversion receiver IC for cdma-2000 mobile handset applications. The RF front-end included a CELL-band low-noise amplifier (LNA), dual-band direct-conversion quadrature I/Q down-converters, and a local-oscillator (LO) signal generation circuit. At 2.7 V, the LNA had a noise figure of 1.2 dB and input third-order intermodulation product (IIP3) of 9 dBm. I/Q down-converters had a noise figure of 4-5 dB and IIP3 of 4-5 dBm and IIP2 of 55 dBm. An on-chip phase-locked loop and external voltage-controlled oscillator generated the LO signal. The receiver RFIC was implemented in a 0.35-/spl mu/m SiGe BiCMOS process and meets or exceeds all cdma-2000 requirements when tested individually or on a handset.     

A low-voltage 5.1-5.8-GHz image-reject receiver with wide dynamicrange

A monolithic 5-6-GHz band receiver, consisting of a differential preamplifier, dual doubly balanced mixers, cascaded injection-locked frequency doublers, and a quadrature local oscillator generator and prescaler, realizes over 45 dB of image-rejection in a mature 25-GHz silicon bipolar technology. The measured single sideband (50 Ω) noise figure is 5.1 dB with an IIP3 of -4.5 dBm and 17-dB conversion gain at 5.3 GHz. The 1.9×1.2 mm² IC is packaged in a standard 32-pin ceramic quad flatpack and consumes less than 50 mW from a 2.2-V supply     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth,the input third intercept point (IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

一种用于超高频RFID阅读器的正交下变频混频器的分析与设计

分析了共用跨导级的正交下变频混频器的性能,包括电压转换增益、线性度、噪声系数和镜象抑制比,分析表明其在电流开关模式下比传统的Gilbert混频器对具有更好的性能.设计并优化了一个基于共用跨导级结构的用于超高频RFID阅读器的正交下变频混频器.在915MHz频段上,该混频器测得12.5dB的转换增益,10dBm的IIP3 ,58dBm的IIP2和17.6dB的SSB噪声系数.芯片采用0.18μm 1P6M RF CMOS工艺实现,在1.8V的电源电压下仅消耗3mA电流.