A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430×240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146×186 μm2 and consumes 5.3 mW power.     

A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer

This paper presents a very robust 6x OSR receiver for 0.2-2 Gb/s binary NRZ signals, introducing an adaptive equalizer that is auto-calibrating on sample data statistics for reliable data recovery in presence of excessive intersymbol interference, noise and crosstalk. The proposed time domain analysis of the data eye obtained with the oversampling architecture is used to tune the equalizer transfer characteristic. The auto-calibration scheme is fully implemented in the digital domain, resulting in a hardware and power efficient architecture with low process-voltage-temperature (PVT) sensitivity. This robust and highly digitized receiver is demonstrated in 0.18 CMOS technology and is able to equalize variable cable losses up to 22 dB @ 1 GHz. The self-adaptive equalizer solution occupies only 0.05 and consumes 9 mW from a 1.8 V supply and can handle up to 20 m 100 Omega STP cable @ 2 Gb/s. The entire receiver consumes 110 mW operating at 2 Gb/s with bit error rates of better than < 10^-12.     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew

A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl mu/m /spl times/ 360 /spl mu/m) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%.     

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10/sup -15/ and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.     

Link reliability for IS-54/136 handsets with different receiverstructures

We estimate link reliabilities for IS-54/136 digital cellular handsets operating with or without an equalizer in urban, suburban, rural, and mountainous environments. We define the reliability of a user's receiver as the probability that the bit error rate (BER) is less than some specified value. The probability is taken over all mobile positions in a cell area and the BER is averaged over multipath fading. Using a range of tools for modeling and simulation of the digital cellular link (transmitter, channel, and receiver), we present an extensive set of results showing the influence of: (1) receiver structures (differential detection with no equalizer, differential detection with selection diversity, or coherent detection with a medium-complexity equalizer); (2) joint distribution of the channel's RMS delay spread and average signal-to-noise ratio (SNR) (this distribution is based on an environment-specific model reported previously); and (3) vehicle speed (0-200 km/h). In all simulations, we assumed a two-path Rayleigh fading channel characterized by: (1) the delay between paths and (2) the ratio of power received from the first path to that from the second path (the RMS delay spread relates to these two parameters). For typical cell sizes, we find that imposing an equalization requirement in IS-54/136 handsets is overly stringent in all environments, except mountainous areas. For these environments, achieving high reliability requires either equalization or other measures, such as smaller cells, directional base-station antennas, or dual-diversity handsets     

A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.     

A 10 Gb/s BiCMOS adaptive cable equalizer

A 10 Gb/s adaptive equalizer IC using SiGe BiCMOS technology is described. The circuit consists of the combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI) for a variety of cable characteristics. The adaptive loop functions using a novel slope-detection circuit which has a characteristic that correlates closely with the amount of ISI. The chip occupies an area of 0.87 mm/spl times/0.81 mm and consumes a power of 350 mW with 3.3 V power supply. This adaptive equalizer is able to compensate for a cable loss up to 22dB at 5 GHz while maintaining a low bit-error rate.     

Semiconductor laser diode optical amplifiers/gates in photonicpacket switching

In this paper, we will describe how semiconductor laser diode optical amplifiers/gates can be used in the photonic packet switching systems based on wavelength division multiplexed (WDM) techniques. First, we show that cross-gain modulation (XGM) can be suppressed when the device is used in the transparent condition of the waveguide material even when the input signal power exceeds +18 dBm. We then discuss an appropriate encoding for the optical signal. Experimental results show that high bit rate Manchester-encoding enables the use of semiconductor laser diode optical amplifiers/gates in the gain condition as well as the transparent condition. Finally, a new photonic packet receiver which utilizes a semiconductor laser diode optical amplifier as a packet power equalizer is proposed. This receiver accepts 17 dB power fluctuation at nanosecond speed for 10 Gb/s Manchester-encoded signal     

Low-noise current optoelectronic integrated receiver with internalequalizer for gigabit-per-second long-wavelength optical communications

An equalizer, which is essential in order to improve the sensitivity of receiver optoelectronic integrated circuits (OEICs) at a gigabit-per-second data rate, has been monolithically integrated on an InP substrate with a p-i-n photodiode and a high-impedance high-electron-mobility-transistor (HEMT) amplifier. The receiver operated up to 1.6 Gb/s and showed low noise current characteristics. The minimum noise current is less than 4 pA/√Hz. The sensitivity calculated from the noise current characteristics is -28.4 dBm for 1.6-Gb/s signals. The receiver chip, which was assembled on a ceramic mount, exhibited a sensitivity of -30.4 dBm at 1.2 Gb/s and 1.3-μm wavelength. The performance is as good as those of receiver OEICs with an external equalizer and sufficient for practical use in gigabit-per-second optical communication system     

Low-complexity MMSE turbo equalization: a possible solution for EDGE

This paper deals with a low complexity receiver scheme where equalization and channel decoding are jointly optimized in an iterative process. We derive the theoretical transfer function of the infinite length linear minimum mean square error (MMSE) equalizer with a priori information. A practical implementation is exposed which employs the fast Fourier transform (FFT) to compute the equalizer coefficients, resulting in a low-complexity receiver structure. The performance of the proposed scheme is investigated for the enhanced general packet radio service (EGPRS) radio link. Simulation results show that significant power gains may be achieved with only a few (3-4) iterations. These results demonstrate that MMSE turbo equalization is an attractive candidate for single-carrier broadband wireless transmissions in long delay-spread environments.     

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10^-12 with 2³¹-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply     

Direct-conversion RF receiver design

The direct-conversion radio-frequency receiver architecture promises superior performances in power, size, and cost over existing superheterodyne-based receivers. The use of direct-conversion receiver (DCR) architecture, however, has been limited due to two well-known problems, namely, the 1/f noise and the direct-current offset noise, to which conventional architectures are less sensitive. This paper analyzes these noise effects on reception performance of a DCR with alternating-current (ac) coupling filter in the receive path. A mathematical treatment of the performance of a DCR is provided. A performance bound of a DCR given its 1/f noise roll-off frequency and ac-coupling filter cut-off frequency is first obtained using vector coding. Then, the performance of a more practical adaptive reception method using a linear equalizer is discussed. Adaptability is especially important in rapidly time-varying channels such as in the wireless environment. The linear equalizer is effective at signal-to-noise ratios (SNRs) below 9 dB, but its performance degrades significantly at larger SNR. To achieve high performance at large SNR (>9 dB), a spectrum shaping method using line codes for direct-conversion reception is proposed. This method achieves near-optimum direct-conversion reception at high SNR while maintaining low complexity and adaptability at the receiver     

Doubly Iterative Equalization of Continuous-Phase Modulation

In this paper, a doubly iterative receiver is proposed for joint turbo equalization, demodulation, and decoding of coded binary continuous-phase modulation (CPM) in multipath fading channels. The proposed receiver consists of three soft-input soft-output (SISO) blocks: a front-end soft-information-aided minimum mean square error (MMSE) equalizer followed by a CPM demodulator and a back-end channel decoder. The MMSE equalizer, combined with an a priori soft-interference canceler (SIC) and an a posteriori probability mapper, forms a SISO processor suitable for iterative processing that considers discrete-time CPM symbols which belong to a finite alphabet. The SISO CPM demodulator and the SISO channel decoder are both implemented by the a posteriori probability algorithm. The proposed doubly iterative receiver has a central demodulator coupled with both the front-end equalizer and the back-end channel decoder. A few back-end demodulation/decoding iterations are performed for each equalization iteration so as to improve the a priori information for the equalizer. As presented in the extrinsic information transfer (EXIT) chart analysis and simulation results for different multipath fading channels, this provides not only faster convergence to low bit error rates, but also lower computational complexity.     

Performance evaluation of experimental 50-Mb/s diffuse infraredwireless link using on-off keying with decision-feedback equalization

We report an experimental nondirected optical link for short-range, indoor data transmission at 50 Mb/s. The system uses on-off keying (OOK) and achieves low bit-error rates (BERs) in the presence of intersymbol interference, background light noise, and shadowing, with a range of 2.9 m in a skylit room. The transmitter produces an eye-safe Lambertian pattern at 806 nm with an average power of 474 mW. The receiver utilizes a hemispherical concentrator with a hemispherical bandpass optical filter, a 1-cm² silicon p-i-n photodiode, and a high-impedance hybrid preamplifier to achieve a high signal-to-noise ratio (SNR). A high-pass filter is used to mitigate fluorescent light noise, with quantized feedback removing the resulting baseline wander. A decision-feedback equalizer provides resistance to intersymbol interference due to multipath. The system and its components are characterized, and compared to theory. We observe that decision-feedback equalization yields a reduction of multipath power penalties that is in good agreement with theory     

A reduced-state soft-statistics-based MAP/DF equalizer for datatransmission over long ISI channels

In this contribution, a novel version of the reduced-state maximum a posteriori probability/decision-feedback (MAP/DF) equalizer for intersymbol interference channels with long impulse responses is presented. The main feature of the proposed equalizer is that the soft statistics generated by the MAP receiver are employed to recursively compute a suitable index of the actual reliability of the (soft) decisions feeding the feedback filter. Therefore, in the presented equalizer, the usual (over-optimistic) assumption of error-free decisions at the input of the feedback filter is relaxed and improved performances are experienced, especially on channels with long impulse responses     

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-μm CMOS

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated     

A Hardware Efficient Passband Equalizer Structure for Data Transmission

A passband digital equalizer is proposed which combines the functions of bandpass filtering and phase splitting with that of adaptive equalization. The new equalizer also provides the in-phase and quadrature outputs required for demodulation. Although input sampling is required at several times the symbol rate (for voice-grade channel applications), outputs need be computed only once per baud. This structure economizes either on front-end analog (phase splitter) filtering or on the number of multiplications required in a digital implementation of a phase splitter and an equalizer. The performance of a receiver incorporating the new equalizer is compared, experimentally, with a receiver using a conventional fractionally spaced (T/2) equalizer.     

Channel Independent Precoder for OFDM-Based Systems Over Fading Channels

In this paper we propose an independent channel precoder for orthogonal frequency division multiplexing (OFDM) systems over fading channels. The design of the precoder is based on the information redistribution of the input modulated symbols among the output precoded symbols. The proposed precoder decreases the variance of the instantaneous noise power at the receiver produced by the channel variability. The employment of an interleaver together with a precoding matrix whose size does not depend on the number of data carriers in an OFDM symbol allows different configurations of time-frequency diversity which can be easily adapted to the channel conditions. The precoder is evaluated with a modified Zero Forcing (ZF) equalizer whose maximum gain is constrained by means of a clipping factor. Thus, the clipping factor limits the noise power transfer in the receiver deprecoding block in low SNR conditions.