Hydrogen-induced piezoelectric effects in InP HEMT's

In this letter, we have investigated hydrogen degradation of InP HEMT's with Ti/Pt/Au gates. We have found that V_T shifts negative after exposure to hydrogen, and exhibits an L_G and orientation dependence. We postulate that ΔV_T is at least in part due to the piezoelectric effect. Hydrogen exposure leads to the formation of TiH_x, producing compressive stress in the gate. This stress induces a piezoelectric charge distribution in the semiconductor that shifts the threshold voltage. We have independently confirmed TiH_x formation under our experimental conditions through Auger measurements. Separate radius-of-curvature measurements have also independently confirmed that Ti/Pt films become compressively stressed relative to their initial state after H₂ exposure     

Titanium hydride formation in Ti/Pt/Au-gated InP HEMTs

Ti/Pt metal layers are an integral part of the gate stack of many GaAs PHEMTs and InP HEMTs. These devices are known to be affected by H ₂ exposure. In this study, Auger Electron Spectroscopy (AES) measurements of Ti/Pt bilayers are correlated with electrical measurements of InP HEMTs fabricated with Ti/Pt/Au gates. The FET measurements show that H₂ exposure shifts the device threshold voltage through the piezoelectric effect. AES reveals the formation of titanium hydride (TiH_x) in Ti/Pt bilayers after identical H₂ exposures. These results indicate that the volume expansion associated with TiH_x formation causes compressive stress in Ti/Pt/Au gates, leading to the piezoelectric effect. After a subsequent recovery anneal in N₂, the FET measurements show that V_T recovers. AES measurements confirm that the TiH_x in hydrogenated Ti/Pt bilayers also decreases after further annealing in N₂     

Electrical characteristics of an optically controlled N-channelAlGaAs/GaAs/InGaAs pseudomorphic HEMT

Electrical characteristics of an n-channel Al_0.3Ga_0.7As/GaAs/In_0.13Ga_0.87 As pseudomorphic HEMT (PHEMT) with L_g=1 μm on GaAs are characterized under optical input (P_opt). Gate leakage and drain current have been analyzed as a function of V_GS, V _DS, and P_opt. We observed monotonically increasing gate leakage current due to the energy barrier lowering by the optically induced photovoltage, which means that gate input characteristics are significantly limited by the photovoltaic effect. However, we obtained a strong nonlinear photoresponsivity of the drain current, which is limited by the photoconductive effect. We also proposed a device model with an optically induced parasitic Al_0.3Ga_0.7As MESFET parallel to the In_0.13Ga_0.87As channel PHEMT for the physical mechanism in the drain current saturation under high optical input power     

增强型InGaP/AlGaAs/InGaAs PHEMT栅退火工艺

针对InGaP/AlGaAs/lnGaAs PHEMT器件,进行了Ti/Pt/Au和Pt/Ti/Pt/Au两种栅金属结构的退火实验,通过实验研究比较,得到了更适用于增强型器件的退火工艺,利用Ti/Pt/Au结构,在320℃退火40min,使器件阈值电压正向移动大约200mV,从而成功制作了高成品率的稳定一致的增强型器件,保证了增强型器件阈值电压在零以上.     

HEMT degradation in hydrogen gas

The effect of hydrogen treatment on both GaAs pseudomorphic HEMT's and InP-based HEMT's, in order to simulate the hermetic seal environment in a Kovar package, is reported for the first time. Under the 270°C, 4% H₂ in Ar atmosphere, significant changes in both types of HEMT's were observed within several minutes. While the drain current at a fixed gate bias and the pinchoff voltage of the GaAs PHEMT consistently decreased under the influence of the hydrogen gas, they were found to either increase or decrease with the InP HEMT. The change of device characteristics resulting from exposure to the hydrogen environment is not permanent; partial recovery of device characteristics was observed under either nitrogen or hydrogen at both elevated and room temperatures. The change in HEMT DC characteristics seems to be primarily resulted from the change in the gate built-in potential. Any device changes due to the Si-donor neutralization by atomic hydrogen, and therefore a reduction in channel carrier concentration, were found to be insignificant     

Effect of Gate Sinking on the Device Performance of the InGaP/AlGaAs/InGaAs Enhancement-Mode PHEMT

An enhancement-mode InGaP/AlGaAs/InGaAs pseudomorphic high-electron mobility transistor using platinum (Pt) as the Schottky contact metal was investigated for the first time. Following the Pt/Ti/Pt/Au gate metal deposition, the devices were thermally annealed at 325 degC for gate sinking. After the annealing, the device showed a positive threshold voltage (V_th) shift from 0.17 to 0.41 V and a very low drain leakage current from 1.56 to 0.16 muA/mm. These improvements are attributed to the Schottky barrier height increase and the decrease of the gate-to-channel distance as Pt sinks into the InGaP Schottky layer during gate-sinking process. The shift in the V_th was very uniform across a 4-in wafer and was reproducible from wafer to wafer. The device also showed excellent RF power performance after the gate-sinking process     

Comparison of photoresponsive drain conduction and gate leakage inn-channel pseudomorphic HEMT and MESFET under electro-opticalstimulations

Photoresponsive drain conduction and gate leakage characteristics of n-channel PHEMT and MESFET are comparatively reported as a function of electro optical stimulation (V_GS, V_DS, P_opt; λ=830 nm). Both in PHEMT and MESFET, a strong nonlinearity of drain photoresponse (R) with P_opt was observed and can be modeled empirically as R=κP_opt^-β (κ_PHEMT≫κ_MESFET) where model parameters κ and β accommodate differences in device/epitaxial structures and electrical biases. Gate leakage current was linearly increasing with P_opt while it was independent of V_DS in both PHEMT and MESFET. However, I_G was a strong function of V_GS in PHEMT while it was almost independent in MESFET due to suppressed modulation of photoresponsive depletion width with heavy channel doping. Photonic gate response (R_pG), on the other hand, was observed to be constant in MESFET while it was a strong function of electrical bias in PHEMT     

0.15-$muhboxm$-Gate InAlAs/InGaAs/InP E-HEMTs Utilizing Ir/Ti/Pt/Au Gate Structure

High-current 0.15-mum-gate enhancement-mode high-electron mobility transistors utilizing Ir/Ti/Pt/Au gate metallization were fabricated using a new process including a high-temperature gate anneal that is required for Schottky-barrier height enhancement for the Ir-based gate contact. SiN_x encapsulation was employed to prevent thermal degradation of device layer during the high-temperature gate anneal. Excellent enhancement-mode operation, with a threshold voltage of 0.1 V and I_DSS of 2.1 mA/mm, was realized. Both the annealed and unannealed devices exhibited high g_m,max and I_D,max of 800 mS/mm and 430 mA/mm, respectively. A unity current-gain cutoff frequency f_T of 151 GHz and a maximum oscillation frequency f_MAX of 172 GHz were achieved. From the dc and RF characteristics, it can be deduced that there was no degradation of the gate contact and the heterostructure due to gate annealing. Furthermore, it was found that the gate diffusion during gate annealing was negligible since no increase in g_m,max was observed     

A novel technology to reduce the antenna charging effects duringpolysilicon gate electron-cyclotron-resonance etching

A novel technique, which uses Cl₂/O₂ mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl₂ /O₂ can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E_bd degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl₂/O₂ mixed gas     

Work Function Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices

A lanthanum (La)-doped HfN is investigated as an n-type metal gate electrode on SiO₂ with tunable work function. The variation of La concentration in (HfinfinLa_1-x)N_y modulates the gate work function from 4.6 to 3.9 eV and remains stable after high-temperature annealing (900degC to 1000degC), which makes it suitable for n-channel MOSFET application. An ultrathin high-fc dielectric layer was formed at the metal/SiO₂ interface due to the (HfinfinLa_1-x)N_y and SiO₂ interaction during annealing. This causes a slight reduction in the effective oxide thickness and improves the tunneling current of the gate dielectric by two to three orders. We also report the tunability of TaN with Al doping, which is suitable for a p-type metal gate work function. Based on our results, several dual-gate integration processes by incorporating lanthanum or aluminum into a refractory metal nitride for CMOS technology are proposed.     

No blister formation Pd/Pt double metal gate MISFET hydrogen sensors

Blister formation in palladium gate MISFET hydrogen sensors occurs even at low hydrogen pressures and the sensors fail in long-time operation. The blisters in the Pd gate are due to hydrogen-induced lattice expansion of the Pd film. By making a double metal gate of Pd/Pt, the problem is avoided without any loss of the hydrogen sensitivity.     

The role of grain-boundary on the hydrogen-induced degradation inthin-film ferroelectric capacitors

The electrical properties of thin-film ferroelectric capacitors are known to degrade severely when exposed to hydrogen. In this study, we directly measured the effects of the grain boundary on the hydrogen-induced degradation in ferroelectric Pb(Zr, Ti)O₃ (PZT) thin films by the location of the top Pt electrode either inside the grains or at the grain boundary. A strong relationship between the grain boundary and the electrical properties of ferroelectric capacitors as a result of hydrogen annealing was found. The degradation of the electrical properties in thin-film ferroelectric capacitors after hydrogen annealing is mainly due to the presence of the grain boundary in the ferroelectric thin film     

Effect of CVD-SiO/sub 2/ film on reliability of GaAs MESFET with Ti/Pt/Au gate metal

The effect of CVD-SiO/sub 2/ films on the reliability of GaAs MESFET with Ti/Pt/Au gate metal was investigated. It was found that the mean time to failure (MTTF) of MESFET with 350/spl deg/C-depositied SiO/sub 2/ was only about one-seventh of that of the ones with 440/spl deg/C-SiO/sub 2/. It was also found that, in the storage test at 300/spl deg/C for 24 hours, diffusion of Pt into GaAs was accelerated when the SiO/sub 2/ deposition temperature was lower than 380/spl deg/C. FT-IR spectra indicated that the lower deposition temperature leads to a higher concentration of the residual hydrogen in SiO/sub 2/. Thermal differential spectrometry (TDS) demonstrated that hydrogen in SiO/sub 2/ could migrate even below 300/spl deg/C. In conclusion, the residual hydrogen in SiO/sub 2/ causes the degradation phenomena.     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET withreduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C_f^ext) of conventional T-shaped gate HJFET's. By introducing a T-shaped SiO₂-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-μm gate-openings which were suitable for reducing the C_f^ext and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-μm DDS gate HJFETs are fabricated. The 0.1-μm n-Al _0.2Ga_0.8As/i-In_0.15Ga_0.85As pseudomorphic DDS gate HJFETs exhibited an excellent V_th standard-deviation (σV_th) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO₂ passivation film had very high performance with an f_T of 120 GHz and an f_max of 165 GHz, due to the low C_f^ext with the DDS gate structure. In addition, a high f_T of 151 GHz and an f_max of 186 GHz were obtained without a SiO₂ passivation film. This fabrication technology shows great promise for high-speed IC applications     

GaAs surface plasma treatments for Schottky contacts

The properties of different rectifying metallizations (Al, Ti/Pt, WN_x) on GaAs have been investigated for various surface preparation procedures. In particular, in situ hydrogen plasma treatments were used to remove residual surface contamination (mainly O and C) and a nitrogen plasma to grow a thin mixed nitride layer. Al and Ti/Pt Schottky diodes with an ideality factor very close to 1, but with reduced barrier height, were found after the H₂ plasma as a consequence of H diffusion into GaAs. The Schottky barrier height was further reduced if a H₂ + N₂ plasma was performed. The N content in the sputtering environment during the WN_x deposition affects the diode properties of plasma-treated WN_x contacts. By increasing the N₂ partial pressure, the diode barrier height is reduced, probably due to nitridization of the GaAs surface. Such differences disappear after annealing the diodes in arsine overpressure at 800°C. WN_x contacts deposited under different conditions on H₂ plasma treated substrates also show a similar Schottky barrier height after such annealing.     

Stable gallium arsenide MIS capacitors and MIS field effecttransistors by (NH4)2Sx treatment andhydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH₄)₂S_x chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550°C is shown to be the key process for achieving midgap interface state density below 10 ¹¹/cm²/eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH₄)₂S_x treated GaAs substrate using gate dielectrics such as PECVD SiO ₂ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g_ms measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g_ms is almost absent in the devices fabricated on (NH₄)₂S_x-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH₄)₂S _x treatment     

Enhancement-mode high electron mobility transistors (E-HEMTs)lattice-matched to InP

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 μm. A maximum extrinsic transconductance (g_mext) of 701 mS/mm and a threshold voltage (V_T) of 167 mV was measured for 0.3 μm gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f _t) of 116 GHz was measured as well as a maximum frequency of oscillation (f_max) of 229 GHz for 0.3 μm gate-length E-HEMTs     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation