CHARACTERISTICS OF METAL-FERROELECTRIC-INSULATOR-SILICON DEVICES USING HFSION BUFFER LAYERS

ABSTRACT

In this work, metal-ferroelectric-insulator-silicon (MFIS) devices were fabricated using HfSiON as buffer layers and their electrical properties were studied. Ultra-thin HfSiON films were fabricated by electron-beam evaporation at room temperature and post-annealed using different parameters such as temperature, time in O₂. By annealing a 2 nm-thick HfSiON film at 800°C for 60s in O₂, a negligible hysteresis loop and small equivalent oxide thickness of 2.3 nm were obtained with a corresponding leakage current density of 6.8 × 10^{? 5} A/cm² at a voltage shifted from the flat band voltage by 1 V. In the fabrication of MFIS diodes, Sr_0.8Bi_2.2Ta₂O₉ (SBT) films with 400 nm thickness were formed by chemical solution deposition. For Pt/SBT (400 nm)/HfSiON(2 nm)/Si diodes, a memory window of 0.8 V in width was observed during double capacitance-voltage sweep between +5 and –5 V. At the same time, excellent data retention properties were observed. The high and low capacitances in the hysteresis loop were well distinguishable even after 24 h had elapsed.     

Fabrication of MFIS diodes using sol-gel derived SBT films and LaAlO3 buffer layers

Abstract

We demonstrate the ferroelectric behavior of Sr_0.8Bi_2.2Ta₂O₉ (SBT) films grown on Si(100) substrates by using lanthanum aluminate (LaAlO₃) buffer layers. LaAlO₃ films were prepared by vacuum evaporation method. Then, they were subjected to ex situ dry N₂ annealing in a rapid thermal annealing (RTA) furnace. From the capacitance-voltage (C-V) measurement, the dielectric constant of LaAlO₃ was estimated to be 20～25. On these substrates, SBT films (210nm) were deposited by sol-gel method and they were characterized by XRD analysis after annealing under various conditions. It was found from C-V characteristics that the memory window of an SBT film annealed at 750°C for 30min in O₂ atmosphere was about 3.0V for the voltage sweep of ±10V. It was also found from the retention measurement that the capacitance values of the SBT film annealed at 750°C did not change over 12hours. It is concluded from these results that the SBT/LaAlO₃/Si(100) structure is one of the most promising structures for realizing MFISFETs (metal-ferroelectric-insulator-semiconductor field-effect-transistors).     

Characterization of the CeO2 thin films for insulation layer and Pt/SrBi2Ta2O9/CeO2/Si MFISFET structure

Abstract

CeO₂ and SrBi₂Ta₂O₉ (SBT) thin films for MFISFET (metal-fcrroelectrics-insulator-semiconductor field effect transistor) were deposited by rf sputtering and pulsed laser deposition method, respectively. The effects of oxygen partial pressure during deposition for CeO₂ films were investigated. The oxygen partial pressure significantly affected the preferred orientation, grain size and electrical properties of CeO₂ films. The CeO₂ thin films with a (200) preferred orientation were deposited on Si(100) substrates at 600°C. The films deposited under the oxygen partial pressure of 50 % showed the best C-V characteristics among those under various conditions. The leakage current density of films showed order of the 10^?7～10^?8 A/cm² at 100 kV/cm. The SBT thin films on CeO₂/Si substrate showed dense microstructure of polycrystalline phase. From the C-V characteristics of MFIS structure composed of the SBT film annealed at 800°C, the memory window width was 0.9 V at ±5 V. The leakage current density of Pt/SBT/CeO₂/Si structure annealed at 800°C was 4×10^?7 A/cm² at 5 V.     

Analysis of read-out operation in 1T2C-type ferroelectric memory cell

Abstract

A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO₂/Si interface, was fabricated and characterized. It was found that the memory window significantly changed by the device parameters, which means that the low voltage operation is possible if we optimize these parameters. The fabricated cell, is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO₂/Si with the area ratio of the MOS capacitor to the ferroelectric capacitor of 6 or 10. Nonvolatile memory operation was confirmed, in which the current on/off ratio was larger than 3-order-of magnitude and the data retention time was longer than 6 × 10⁴ seconds.     

MFIS and MFMIS structures using Pb(Zr,Ti)O3 films for nonvolatile memory devices

Abstract

In this work, metal / ferroelectric / insulator / semiconductor (MFIS) and metal / ferroelectric / metal / insulator / semiconductor (MFMIS) structures using Pb(Zr, Ti)O₃ (PZT) films were fabricated and characterized for nonvolatile NDRO memory device. 300nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO₄(ZT)/Si and Pt/ZT/Si substrates. C-V hysteresis were measured in both MFIS and MFMIS structures. By using a small-size MFM capacitor on a large-size MIS structure, it was found that the memory window of MFMIS structure was larger than that of the MFIS structure. There is a critical area ratio (S_MIS/S_MFM) in MFMIS structure. When an area ratio in MFMIS structure is below 12, the memory window increased with increasing area ratio. We could obtain that the memory window of MFMIS structure with a S_MIS/S_MFM of 11.8 was 2.1 V and 3.2 V with an applied voltage at 3 V and 5 V.     

Low temperature preparation of ferroelectric SrBi2Ta2O9 thin films by a modified RF magnetron sputtering technique

Abstract

Bi–layered ferroelectric SrBi₂Ta₂O₉ (SBT) films were successfully prepared on Pt/Ti/SiO₂/Si substrates at 650°C by a modified rf magnetron sputtering technique. The SBT films annealed for 1 h in O₂ (760 torr) and again for 30 min in O₂ (5 torr) at 650°C show a average grain size of about 49 nm. The SBT films annealed at 65 0°C have a remanent polarization (P_r) of 6.0 μC/cm² and coercive field (E_c) of 36 kV/cm at an excitation voltage of 5 V. The films showed fatigue–free characteristics up to 4.0 × 10¹⁰ switching cycles under 5 V bipolar pulse. The retention characteristics of SBT films looked very promosing up to 1.0 × 10⁵ s.     

Preparation of SrBi2Ta2O9 ferroelectric thin film by rf magnetron sputtering

Abstract

SrBi₂Ta₂O₉ (SBT) thin films were deposited on 6-inch Pt/Ti/SiO₂/Si substrates by rf magnetron sputtering using a 12-inch ceramic SBT single target. It is found that several sputtering parameters such as argon (Ar) pressure and rf power were very effective to control the Bi content of SBT thin films which is essential for obtaining good ferroelectric properties.     

Integration of H2 barriers for ferroelectric memories based on SrBi2Ta2O9 (SBT)

Abstract

In this study, integration of an hydrogen barrier into a FeRAM process flow is investigated. It is reported in the literature that ferroelectric properties can be maintained after hydrogen annealing by using IrO_x as a top electrode [16][17][18]. Advantage of materials like IrO_x is less catalytic activity compared to Pt. However, we found that IrO_x is not a promising candidate for top electrode barrier. (Pt)/IrO_x/SBT/Pt capacitors are prone to shorting or exhibit high leakage. IrO_x films are very easily reduced by reducing ambient which will result in peeling off. Also, IrO_x films tend to oxidize Ti or TiN layers immediately. Therefore, other barrier materials or layer sequences like Ir/IrO_x have to be considered.

For protection of the entire capacitor an Encapsulation Barrier Layer (EBL) is required. In this study, LPCVD SiN is used. LPCVD SiN is a standard material in CMOS technology. Production tools are available and it is well known as hydrogen barrier. By modifying the deposition process and using a novel process sequence, no visual damage of the capacitors after SiN-deposition and FGA is seen. Also, no degradation of electrical properties after capacitor formation as well as after SiN-deposition and FGA is observed. However, after metal 1 and metal 2 processing, 2P_r values at 1.8V are reduced from 12μC/cm²to 2μC/cm². Polarization at 5.0V is not affected.     

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices

Abstract

We have investigated the roles of buffer layer in the Pt/SBT-Y₂O₃/p-Si (MFIS) capacitors. We found that the insertion of Y₂O₃ buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However, negative charges with the effective density of 3.21×10¹²/cm² were generated due to the additional process step for Y₂O₃ deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y₂O₃ buffer layer minimize the charge injection, the shift of the hysteresis loops was asymmetrical.     

Integration and characterization of MFISFET using Pb5Ge3O11

Abstract

The first MFIS FETs PMOS using Pt/Pb₅Ge₃O₁₁/ZrO₂/n-Si structure has been successfully fabricated. The PGO thin film was deposited by spin on method. Single phase PGO with strong c-axis orientation and low leakage current was obtained on ZrO₂ substrate. Pt was used as top electrode and the gate stack was dry etched using chlorine chemistry. Using CMOS compatible process, the integration of MFIS FETs is simple and reliable. I_D-V_G and I_D-V_D were characterized on 10 × 10 μrn (L × W) devices. The memory window obtained is about 1.3V with 200nm PGO and 13nm ZrO₂. It is also found that memory window is less dependent on device sizes.     

The role of buffer layer in strontium bismuth tantalate based ferroelectric gate mos structures for non-volatile non destructive read out memory applications

Abstract

Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO₂) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO₂ film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.     

Effects of Substrate and Annealing Temperatures on the Characteristics of SrBi4Ti4O15 Thin Films

In this study, radio frequency (RF) sputtering was used as the method and the layer-structured bismuth compound of SrBi₄Ti₄O₁₅ + 4 wt% Bi₂O₃ ferroelectric ceramic was used as the target to deposit the SrBi₄Ti₄O₁₅ (SBT) thin films. The addition of excess Bi₂O₃ content in the target ceramic was used to compensate the vaporization of Bi₂O₃ during the sintering and deposition processes. SBT ferroelectric thin films were deposited on Pt/Ti/SiO₂/Si under optimal RF magnetron sputtering parameters with different substrate temperatures for 2 h. After that the SBT thin films were post-heated using rapid temperature annealing (RTA) method. The dielectric and electrical characteristics of the SBT thin films were measured using metal-ferroelectric-metal (MFM) structure. From the physical and electrical measurements of X-ray diffraction pattern, scanning electronic microscope (SEM), I-V curve, and C-V curve, we had found that the substrate temperature and RTA-treated temperature had large influences on the morphology, the crystalline structure, the leakage current density, and the dielectric constant of the SBT thin films.     

Ferroelectric properties of SrBi2Ta2O9 thin films on Si (100) with a LaZrO x buffer layer

To obtain a metal–ferroelectric–insulator–semiconductor (MFIS) structure, we fabricated ferroelectric SrBi₂Ta₂O₉ (SBT) film on a p-type Si (100) wafer with a LaZrO _x (LZO) buffer layer by means of a sol–gel technique. The sol–gel deposited LZO film according to the different annealing temperatures had a good surface morphology even though the crystalline phase was not an amorphous phase. In particular, the root-mean-squared (RMS) surface roughness of the 750-°C-annealed LZO film was about 0.365 nm and its leakage current density was about 8.2?×?10^?7 A/cm² at 10 V. A Au/SBT/LZO/Si structure with different SBT film was fabricated. The C–V characteristics of the Au/SBT/LZO/Si structure showed a clockwise hysteresis loop. The memory window width increased as the SBT film thickness increased. The 600-nm-thick SBT film was crystallized in a polycrystalline phase with a highly preferred (115) orientation. The memory window width of the 600-nm-thick SBT film was about 1.94 V at the bias sweep voltage ±9 V and the leakage current density was about 6.48?×?10^?8 A/cm² at 10 V.     

Ferroelectric-Gate Field Effect Transistors Using (Y,Yb)MnO3/Y2O3/Si(111) Structures for 1T-Type FeRAMs

Fabrication and characterization of metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFIS FETs) using (Y,Yb)MnO₃/Y₂O₃/Si structures were introduced for the first time. P-channel MFIS FETs were fabricated on n-type Si(111) substrates, in which an Y_0.5Yb_0.5MnO₃(200 nm)/Y₂O₃(25 nm) structure was used as gate insulator. The Y_0.5Yb_0.5MnO₃ and Y₂O₃ films were prepared by chemical solution deposition. A fabricated MFIS FETs showed the hysteresis loop due to spontaneous polarization in the I_D-V_GS characteristic, in which the memory window was about 0.9V when the applied gate voltage was swept between 8 V and ?8 V. Especially, the alternative drain current was retained after applying a single voltage pulse with a magnitude of +9 V or ?9 V.     

Inverse Capacitance-Voltage Characteristics of Bi3.25La0.75Ti3O12 Thin Film Pulsed Laser Deposited on Thermally Oxidized n-Type Si Substrates

Comparative studies on the electrical properties of a metal-ferroelectric-insulator-semiconductor field effect transistor were conducted using pulsed laser ablated ferroelectric Bi_3.25La_0.75Ti₃O₁₂ (BLT) thin films deposited on SiO₂/Si substrates with different SiO₂ thicknesses. The SiO₂ layer was prepared on n-type Si substrates by dry oxidation at a temperature of 800°C. Small angle x-ray reflectivity studies were used to measure the SiO₂ thickness. The capacitance-voltage (C-V) measurements revealed that the films showed good interfacial properties. Shifts in flatband voltages were observable, but were effectively reduced by deposition of the ferroelectric films. Au/BLT/SiO₂/Si diodes with 8 nm SiO₂ layer showed to be stable with relatively large memory window values of about 0.3 V, 2.5 V, 5.0 V, and 7.0 V, at increasing bias voltages of ±5 V, ±7 V, ±10 V, and ±12 V, respectively.     

Characterization of Au/Pb(Zr0.96Ti0.04)O3/Al2O3/Si antiferroelectric field-effect transistors for memory application

Polarization-voltage (P-V) hysteresis loops and polarization retention were studied for Au/Pb(Zr_0.96Ti_0.04)O₃/Al₂O₃/Pt antiferroelectric capacitors with different Al₂O₃ layer thicknesses. The high-field ferroelectric phase after poling can be pertained to zero external field with the choice of an appropriate Al₂O₃ layer thickness. At the same time, a strong depolarization field across the Al₂O₃ layer is generated with the direction opposite to the field across the Pb(Zr_0.96Ti_0.04)O₃ layer. The depolarization-field direction can be reversed with the domain switching of the high-field ferroelectric phase, possessing the potential application of antiferroelectric memories. A large memory window of 10 V was observed for Au/Pb(Zr_0.96Ti_0.04)O₃ (50 nm)/Al₂O₃ (6.3 nm)/n-Si (100) field-effect transistors, as confirmed from the capacitance sweeping under voltages between ?19 and +19 V. The high/low capacitance ratio is over 8:1, and the ratio remains stable with time over 4 h after programming voltage of ±19 V at 80°C, in suggestion of the excellent retention of the memory.     

Growth and characterization of non-c-axis-oriented SrBi2Ta2O9 epitaxial thin films on Si(100) substrates with SrRuO3 bottom electrodes

Abstract

We have successfully grown non-c-axis-oriented epitaxial ferroelectric SrBi₂Ta₂O₉ (SBT) films with (116) and (103) orientations on Si(100) substrates using epitaxial (110)- and (111)-oriented SrRuO₃ (SRO) bottom electrodes, respectively. The SRO orientations have been induced by coating the Si(100) substrates with epitaxial YSZ(100) and MgO(111)/ YSZ(100) buffer layers, respectively. All films were sequentially grown by pulsed laser deposition. Specific in-plane orientations of the epitaxial SBT films were found, which are in turn determined by specific in-plane orientations of the epitaxial SRO bottom electrodes. These include a diagonal rectangle-on-cube epitaxy of SRO(110) on YSZ(100) and a triangle-on-triangle epitaxy of SRO(111) on MgO(111).     

Low-Temperature Process of Ferroelectric (Y0.95,Bi0.05)MnO3 Thin Films and Their Structural and Electrical Properties

[(Y_0.95,Bi_0.05)MnO₃] (YBM) films have been grown on Y₂O₃ buffered Si (001) by pulsed-laser deposition (PLD). We have compared the structural and dielectric properties of YBM films with those of typical YMnO₃ films from the viewpoint of lowering the process temperature. The highly c-axis oriented YBM film have been obtained on Y₂O₃/Si (001) at 700°C, which is a significantly reduced growth temperature from that of typical YMnO₃ films (850°C). The Bi modification was effective for the low temperature processing of YBM films. These highly c-axis oriented YBM films was obtained only at high ambient oxygen pressures, for example above 100 mTorr, contrary to YMnO₃ films which requires low ambient oxygen pressure for the growth of c-axis preferred orientation. The dielectric constant and dissipation factor was 29 and 0.017 at 1 MHz, respectively. The memory window due to ferroelectric polarization switching was found in a capacitance-voltage (C-V) characteristic. The YBM/Y₂O₃/Si structure with above characteristics of YBM films exhibited the C-V memory window of 1.2 V at a sweep voltage of 5 V. The flat-band voltage shifted symmetrically with increasing the sweep voltage up to 8 V due to little charge injection from Si. As a result, the memory window increased progressively with increasing the sweep voltage and amounted to 2 V at a sweep voltage of 8 V. The leakage current density was below 5 × 10^?7 A/cm² at a bias voltage of 8 V.     

Investigation on various insulator layers for MFIS capacitors

Abstract

Effects of insulator layers of Metal(Au)/Ferroelectrics(PZT)/Insulator/Si (MFIS) structure capacitors are investigated for non-destructive type non-volatile memory device applications. Various high dielectric oxide layers such as Al₂O₃, Ta₂O₅, TiO₂ and ZrO₂ were fabricated by reactive sputtering as insulating layers. The oxide insulators give significant impacts on the morphologies of PZT layer and the properties of capacitors. It is noted that the oxide layers with small thermal expansions (<6x10^–6/°C) coefficient caused cracks on PZT films during PZT crystallization annealing. The effects of insulators as a diffusion barrier are also comparatively studied using Auger electron spectroscopy. In addition, the characteristics of high dielectric solid solution, such as titanium oxide-zirconium oxide, are also studied.     

Distributed phase shifters using (Ba,Sr)TiO3 thin films on sapphire and glass substrates

Abstract

Sol-gel solutions were synthesized by using various alkoxides of polyhydric alcohol, carboxylate and stabilizer. Stability of modified sol-gel solution was good enough to keep its properties after at least three months although that of ordinary sol-gel solution is not good.

SBT films were fabricated on Pt(200nm)/Ti(20nm)SiO₂(500nm)/Si substrate at under 700°C by using modified sol-gel solution. Range of drying temperature was 200 to 400°C and that of RTA was 550 to 700°C. At high drying temperature, decrease of crystallinity for SBT films was observed accompanied by nucleation of Sr carbonate. On the other hand, SBT film dried at under 250°C and crystallized at 700°C shows high crystallinity of layer perovskite.

SBT film derived from conventional sol-gel solution used to show strong crystal orientation of c-axis. In case of modified sol-gel solution, RTA temperature and amount of added stabilizer influenced crystal orientation of film. So it was possible that to control crystal orientation of SBT films by adjust RTA condition and amount of stabilizer. Stability of sol-gel solution and property of SBT films were influenced by component of solvent, electric properties of SBT films especially I-V property were improved.

Using low temperature deposition process at 650°C, SBT films derived from modified sol-gel solution show superior ferroelectric properties to SBT thin films derived from conventional MOD solution.