I-V characteristics of a ferroelectric field effect transistor

Abstract

There are many possible uses for ferroelectric field effect transistors. To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a FFET are described from empirical data. The effective gate capacitance and charge are derived from experimental data on an actual ferroelectric transistor. A general equation ^[1] for a MOSFET is used to derive the internal characteristics of the transistor. Experimental data derived from a Radiant Technologies^[2] FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations.

The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material. Two polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse. The transistor is also simulated using a mathematical model from earlier research ^[3]. This model accurately predicts the I-V characteristics of the transistor.     

考虑变温度影响的SiC MOSFET建模与分析

为了准确反映SiC MOSFET在不同温度下的电气特性,对影响SiC MOSFET电气特性的关键参数进行了分析,提出了一种SiC MOSFET等效电路模型。首先,根据SiC MOSFET阈值电压和跨导随温度变化的规律,采用函数拟合的温控电源模型对SiC MOSFET的阈值电压和漏极电流进行补偿;其次,考虑寄生电容与极间电压的关系,采用电容子电路和可变电容模型对SiC MOSFET的寄生电容进行等效模拟,根据SiC MOSFET体二极管对其静、动态特性的影响,利用独立二极管模型描述体二极管特性,进而建立SiC MOSFET的等效电路模型。最后,在不同温度条件下,对该模型进行了仿真并与实验测试结果进行了对比。结果表明所建模型较为准确地描述SiC MOSFET在较宽温度范围内的静、动态特性,验证了模型的有效性。     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis of the floating‐gate transistor using the charge sheet model

The multiple‐input floating‐gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple‐input floating‐gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple‐input floating‐gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

A macromodel of sample-and-hold circuits

A concise macromodel of sample-and-hold circuits for the simulator SPICE is proposed. This generalized model is independent from actual technical realizations and is based upon compromises regarding the representation of exact circuit structures in the model. Different types of feedback and hold capacitor connections corresponding to the standard external circuit application are accounted for in the model internally. The macromodel allows one to simulate arbitrary user circuits with respect to the behaviour in both the time and frequency domains including error parameters and the temperature dependence of several parameters. Model parameters are extracted for the integrated sample-and-hold circuit AD585 from Analog Devices as an example. Simulation results and selected diagrams are compared with the manufacturer's data. © 1997 by John Wiley & Sons, Ltd.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

This paper presents physics based analytical model for center potential, electric field and subthreshold drain current of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG). The expressions are derived from Poisson's equation in cylindrical co‐ordinate system based on parabolic potential approximation (PPA). The influence of technology parameter variations such as gate length, silicon pillar diameter and oxide thickness on electrical characteristics is studied in detail. Developed analytical model results are validated through the good agreement with simulated data obtained from ATLAS 3D simulator. Copyright © 2016 John Wiley & Sons, Ltd.     

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFETs in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The devices were only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The designs consist of a small array of logic gates. Other gates could easily be produced. They are linked by FFETs that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.     

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

Scaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits. Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.     

基于WARD等值的电网限流运行方式优化方法

控制短路电流水平,保证断路器安全是电网运行方式安排的重要任务。线路开断及母线分裂以增大变电站母线与电源之间的电气距离是限制电网短路电流水平的有效措施,但同时也可能引起电网运行可靠性水平的降低。首先根据对网络拓扑结构的分析及线路开断前后超标站点的短路电流变化确定可开断支路集;然后添加功率平衡方程约束、支路潮流约束以及N-1安全约束;以开断线路数最少为目标,提出了控制短路电流水平的电网运行方式优化模型,并借助WARD等值缩小模型规模,提高了模型的求解效率。所提模型为混合整数线性规划模型,可以采用线性规划单纯形法及分支定界法迅速求解。使用C++编写了仿真程序,通过对IEEE39节点系统和某实际电网的仿真分析验证了所提模型的正确性和算法的有效性。     

A Gate‐Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

A gate leakage current model for advanced MOSFETs has been developed and implemented into the Hiroshima‐university STARC IGFET Model (HiSIM), the first complete surface‐potential‐based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Comparison of modeling techniques in circuit variability analysis

Three nonlinear reduced‐order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal‐oxide‐semiconductor technologies where variability of the electrical characteristics of a transistor can be significantly detrimental to circuit performance. The drain currents of 65 nm N‐type metal‐oxide‐semiconductor and P‐type metal‐oxide‐semiconductor transistors are modeled in terms of a few process parameters, terminal voltages, and temperature using Kriging‐based surrogate models, neural network‐based models, and support vector machine‐based models. The models are analyzed with respect to their accuracy, establishment time, size, and evaluation time. It is shown that Kriging‐based surrogate models and neural network‐based models can be generated with sufficient accuracy that they can be used in circuit variability analysis. Numerical experiments demonstrate that for smaller circuits, Kriging‐based surrogate modeling yields results faster than the neural network‐based models for the same accuracy whereas for larger circuits, neural network‐based models are preferred as, in all metrics, better performance is obtained. Within‐die variations for an XOR circuit are analyzed, and it is shown that the nonlinear reduced‐order models developed can more effectively capture the within‐die variations than the traditional process corner analysis. Copyright © 2011 John Wiley & Sons, Ltd.     

Analysis and reduction of radiated EMI noise from converter systems

It is well known that high dv/dt rates on switching devices are the source of EMI noise. This paper describes a mechanism and reduction methods of radiated EMI noise on IGBTs. The radiated EMI noise is generated by oscillating current flowing through the IGBT's output capacity and the snubber circuit, which we call equivalent circuit of radiated EMI noise. The oscillating current of the equivalent circuit is forced to flow by high dv/dt rates of IGBT switching operation. Radiated EMI noise can be analyzed by frequency evolution of oscillating current. The results of this analysis show the relationship of high‐frequency impedance of the equivalent circuit to radiated EMI noise, as well as the behavior of the IGBT's switching voltage waveform. In addition, it is indicated that using a di/dt control gate drive circuit is effective as a means for reducing radiated EMI noise. It is clarified that the standard for industrial equipment of CISPR can be satisfied by using the proposed gate drive circuit. The effects of the method have been verified by experimental and simulational results. © 1999 Scripta Technica, Electr Eng Jpn, 130(1): 106–117, 2000     

Dual Three-Winding Transformer Equivalent Circuit Matching Leakage Measurements

An equivalent circuit for the leakage inductance of three-winding transformers is presented. The model is derived from the principle of duality (between electric and magnetic circuits) and matches terminal-leakage inductance measurements. The circuit consists of a set of mutually coupled inductances and does not contain negative inductances. Each inductance can be computed from both: the geometrical information of the windings and from terminal-leakage measurements taking two windings at a time. The new model is suitable for steady state, electromechanical transients, and electromagnetic transient studies. The circuit can be assembled in any circuit simulation program, such as EMTP, PSPICE, etc. programs, using standard mutually coupled inductances.      

A matrix pencil approach to the local stability analysis of non‐linear circuits

This paper addresses local stability issues in non‐linear circuits via matrix pencil theory. The limitations of the state–space approach in circuit modelling have led to semistate formulations, currently framed within the context of differential‐algebraic equations (DAEs). Stability results for these DAE models can be stated in terms of matrix pencils, avoiding the need for state–space reductions which are not advisable in actual circuit simulation problems. The stability results here presented are applied to electrical circuits containing non‐linear devices such as Josephson junctions or MOS transistors. Copyright © 2004 John Wiley & Sons, Ltd.     

一种无通信的无线电能传输阻抗匹配方法

磁耦合谐振式无线电能传输系统由于线圈两侧的电气隔离,通常使用无线通信来实时获取原副边的电压电流信息并对其进行控制。在一些特殊应用场合比如航天器,由于频率管制等原因无法使用通信电路。为了解决该问题同时使得系统的传输效率最优,提出了一种无通信的阻抗匹配方法。该方法选用Buck电路作为阻抗匹配网络,在负载电压变化时采用线性拟合的方法对整流输出电压进行控制,进而实现对系统最大效率的跟踪。建立了系统的等效电路模型,在不同负载下对系统的效率曲线进行了分析,给出了系统的控制策略。仿真与实验表明,在10cm的传输距离下系统的效率保持87%以上,验证了无通信阻抗匹配方法的可行性。     

基于电压、电流不平衡度差值的干式变压器匝间短路故障识别方法

干式变压器绕组发生轻微匝间短路时,相电压、相电流等电气量变化甚微,不能作为表征匝间短路故障的敏感特征量,导致相应保护措施缺失,运行过程中设备烧毁事故时有发生。通过建立干式变压器“场-路”耦合仿真模型,利用实际试验和工程计算获取的状态参数,验证模型的准确性。通过建立和分析其绕组匝间短路故障数学模型,提取相电压、相电流不平衡度标幺值的差值,作为判断匝间短路故障的特征量。通过仿真分析不同工况下其绕组发生匝间短路故障时不同电气量的变化情况,论证了所提新故障特征量不仅能提前感知绕组匝间短路故障,而且能够克服固有的三相不对称及不平衡运行带来的影响,有效性、灵敏性兼顾,为实时监测干式变压器绕组匝间绝缘状态提供一种新方法。     

Analysis of a self‐regulated,self‐excited,brushless three‐phase synchronous generator,which includes the effect of core losses

This paper presents a novel analysis of a self‐regulated, self‐excited, brushless three‐phase synchronous generator, which includes the effect of core losses. The core losses are modeled by equivalent core loss resistances connected to additional windings on the generator's magnetic coupling model. A magnetic circuit is drawn from the magnetic coupling model, and an electrical equivalent circuit of the generator is derived by utilizing a duality between the magnetic and electric circuits. Using this equivalent circuit, the generator's steady‐state performance is theoretically predicted, and the results are verified through experiment. In addition, the power losses during power generation are analyzed quantitatively. The proposed analysis takes into account the nonlinearity of the exciting impedances due to magnetic saturation. © 2000 Scripta Technica, Electr Eng Jpn, 131(2): 51–60, 2000