Electronic model of a Ferroelectric Field Effect transistor

Abstract

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. The input and output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and are compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.     

FERROELECTRIC GATE FET MEMORY BASED ON CONDUCTION OF FERROELECTRIC-INSULATOR INTERFACE

ABSTRACT

A new type of ferroelectric gate field effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between ferroelectric and insulator layers and needs no semiconductor. This FET consists of source and drain electrodes on ferroelectric film (Pb(Zr_0.52Ti_0.48)O₃(PZT)) prepared on Pt/TiO₂/SiO₂/Si substrate, and gate electrode on HfO₂ insulator film on the PZT film between the source and the drain electrodes. Drain current flows through the interface of the ferroelectric and the insulator. Drain current versus gate voltage characteristics shows clockwise hysteresis loop similarly to the conventional p-channel FET with ferroelectric gate. The FET shows that the On/Off ratio of the conduction current is about 10⁵ and the Off state current is about 10^{? 10}A.     

Analysis of read-out operation in 1T2C-type ferroelectric memory cell

Abstract

A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO₂/Si interface, was fabricated and characterized. It was found that the memory window significantly changed by the device parameters, which means that the low voltage operation is possible if we optimize these parameters. The fabricated cell, is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO₂/Si with the area ratio of the MOS capacitor to the ferroelectric capacitor of 6 or 10. Nonvolatile memory operation was confirmed, in which the current on/off ratio was larger than 3-order-of magnitude and the data retention time was longer than 6 × 10⁴ seconds.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Modeling of metal-ferroelectric-semiconductor field effect transistor subthreshold current

Abstract

A subthreshold current model for metal-ferroelectric-semiconductor field effect transistor (MFSFET) is derived from a new analytical ferroelectric hysteresis model,^1.2 the semiconductor surface model,³ the classical diffusion current model,⁴ as well as the Maxwell equations. The model predicates the shift of MFSFET subthreshold current between forward sweep and backward sweep of gate bias. The simulation results show the effects of coercive voltage, the remanent polarization, the saturation polarization, and the free interface charge between ferroelectric and semiconductor. The external field effect on the saturation polarization (better known as ferroelectric space charge effect) is also modeled. The conventional method to evaluate the interface trapped charge for metal-oxide-semiconductor system is also proposed for MFS system based on the ideal subthreshold current model and its experimental data.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Fabrication and Characterization of Gate-Connected 1T2C-Type Ferroelectric Memory with Paired Bi4 − xLaxTi3O12 Capacitors

A gate-connected 1T2C-type ferroelectric memory, in which the bottom electrodes of paired ferroelectric capacitors are connected to the gate electrode of an underlying FET (field effect transistor) on the field oxide region, was fabricated using a Bi_{4 ? x}La_xTi₃O₁₂ (BLT) film and its electrical properties were characterized. The I_D-V_G (drain current-gate voltage) characteristics of a FET combined with a single ferroelectric capacitor showed that the paired capacitors had almost the same ferroelectric property. It was found in the readout operation that there existed an optimum voltage to maximize the drain current on/off ratio between datum ‘1’ and datum ‘0,’ and that the maximum ratio was as large as 6 × 10⁴. It was also found that the drain current level remained constant, even if the readout operation was repeatedly conducted. It was concluded from these results that the 1T2C-type memory was successfully fabricated using the proposed process and operated properly.     

Ferroelectric memory FET with Ir/IrO2 electrodes

Abstract

We proposed a MFMIS structure having a floating gate as a bottom electrode between a ferroelectric thin film and the gate SiO₂. Conventional gate SiO₂ can be used and ferroelectric thin films can be grown on bottom electrodes which have a good matching with the ferroelectric materials due to adopt the MFMIS structure. Ir and IrO₂ on poly-Si were used as floating gate. When a IrO₂ layer was formed between PZT and poly-Si, a high-quality PZT thin film was obtained and the PZT films show no fatigue up to 10¹² cycles of switching pulses. From the I_D-V_G characteristics measurement for 1·2 μm P-ch MFMIS FET, the shift in V_th or the memory window for a bias sweep of ±15V was about 3·3V. The difference of I_D-V_D curves which corresponded to I_D-V_G characteristics were found between before and after a programming pulse was applied.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

寄生电感对于功率MOSFET开关特性的影响

分散在MOSFET栅极、源极、漏极的寄生电感由于封装以及印制电路板（PCB）走线,改变了MOSFET的开关特性。通过仿真分析对比,指出MOSFET寄生电感存在如下特性：源极电感对栅极驱动形成负反馈,导致开关速度变慢,采用开尔文连接,可以将栅极回路与功率回路解耦,提高驱动速度;在米勒效应发生时刻需要合理地降低栅极电感来降低栅极驱动电流;漏极电感通过米勒电容影响MOSFET的开通速度,在关断时刻导致电压应力增加;在并联的回路当中,非对称的布局将导致MOSFET之间的动态不均流;当MOSFET在开关过程中,环路电感与MOSFET自身的结电容产生振荡时,可以在电路增加吸收电容减小环路电感,改变振荡特性。     

Band structure effect on the electron current oscillation in ultra-scaled GaSb Schottky MOSFET: tight-binding approach

This paper explores band structure effect on the quantum transport of a low-dimensional GaSb Schottky MOSFET (SBFET) for the implementation of III–V transistor with a low series resistance. Precise treatment of the full band structure is employed applying sp ³ d ⁵ s ^? tight-binding (TB) formalism. A remarkable distinction between the thickness dependent effective masses extracted from the TB and the bulk values imply that the quantum confinement modifies the device performance. Strong transverse confinement leads to the effective Schottky barrier height increment. Owing to the adequate enhanced Schottky barriers at low drain voltages, a double barrier gate modulated potential well is formed along the channel. The double barrier profile creates a longitudinal quantum confinement and induces drain current oscillation at low temperatures. Significant factors that may affect the current oscillation are thoroughly investigated. Current oscillation is gradually smoothed out as the gate length shrinks down in ultra scaled structure. The results in this paper are paving a way to clarify the feasibility of this device in nanoscale regime.     

BaMgF4 thin film development and processing for ferroelectric FETS

Abstract

A ferroelectric memory field-effect transistor (FEMFET) where a ferroelectric thin film is incorporated directly into the gate structure of the transistor is attractive, because it provides not only nonvolatility, but also nondestructive readout (NDRO). At Westinghouse, we are currently developing a FEMFET using thin film barium magnesium fluoride (BaMgF₄), a ferroelectric material that was discovered in 1969, but was not fabricated in thin film form until 1989. The BaMgF₄ films are grown by evaporation in an ultrahigh vacuum (UHV) chamber on clean Si(100). The natural tendency of these films to grow with the ferroelectric a-axis in the Si(100) plane has been overcome to obtain more random orientation with larger reversible polarization perpendicular to the film. A capping layer (SiO₂) has been found to be essential for process integrability of these BaMgF₄ films. Ti-W metallization produced only a slight reduction in the capacitance-voltage (C-V) memory window. Switching speed of these films has been measured to be 40 to 45 nanoseconds. The first FEMFET fabricated with BaMgF₄ has exhibited 18 Volt memory hysteresis window with better than 10⁵ on/off current ratio for 20 Volt programming.     

PIMOD processing and properties of a LiNbO3-based MFSFET for nonvolatile memories

Abstract

The photo-induced metallo-organic decomposition (PIMOD) process has been successfully used to deposit a lithium niobate thin film acting as the gate oxide of the conventional MFSFET structure. The use of the low-temperature PIMOD process for thin film deposition has increased the device yields of the molybdenum liftoff for small area isolation. The electronic alteration of the properties of the ferroelectric gate transistor was previously shown to be caused by charges in the semiconductor being injected into the ferroelectric film. To prevent this problem, a thin SiO₂ buffer layer was thermally grown on the silicon substrate immediately before lithium niobate deposition. The silicon-lithium niobate interface was stabilized and the charge injection effect was eliminated due to the formation of the buffer layer. The channel current was shown to be greatly altered by the application of voltage pulses between the gate of the device and the substrate. Upon switching, the change in surface conductivity of the semiconductor was the same as that expected for ferroelectric switching.     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.     

Circuit design issues affecting present and future deep sub-micron ferroelectric random-access memories

Abstract

The basic architecture of ferroelectric memories (FeRAMs) is known to be very similar to that of DRAM. Consequently, many design issues for FeRAM are already known from DRAM and have been solved by applying prior DRAM solutions. However, there are also a number of issues that are unique to FeRAM. Often these issues become critical design problems that require innovative circuit-level solutions^[1]. This paper discusses some of the most relevant issues affecting present and future deep sub-micron FeRAMs. In addition, new problems that have to be solved for future FeRAMs are presented.     

DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT

Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.     

Down-scaling limitations in CMOS devices: Is there a role for the ferroelectrics?

Abstract

This paper reviews down-scaling limitations in CMOS devices, with a special emphasis on the possible application of ferroelectric materials. Ultimate limit in reduction of the thickness of gate oxide is found as the most important limitation. The possibility of replacing or enhancing the gate oxide by a ferroelectric material is critically considered in view of the desired properties of the silicon - to - gate insulator interface.     

Process dependent electrical characteristics and equivalent circuit model of sol-gel based PZT capacitors

Abstract

Studies of electrical properties and an equivalent circuit model is developed for ferroelectric PZT(Ti = 60%) thin film capacitors made by sol-gel spin coating with Pt electrodes. The equivalent circuit consists of two major parts: serial space charge capacitors demonstrating surface effects and parallel elements modeling the inner polycrystalline ferroelectric regions. This model is based on device physics which can demonstrate both the measured capacitance voltage characteristics and hysteresis curves. From the model fit to the data, an estimate of the space charge concentration at the surface and inner grain boundary region of 57times;10²⁰ cm^?3 and 1×10¹⁸ cm^?3 respectively is made. Further electrical characterizations such as pulse switching and polarization degradation (fatigue) have also been studied. Using the equivalent circuit, other characteristics such as the switching time can be studied showing its dependence on applied voltage and capacitor area. The applied voltage dependence of fatigue is shown via an empirical equation where the degradation rate is electric field activated.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature

We propose a novel deep gate lateral double diffused metal-oxide-semiconductor (LDMOS) field-effect transistor in partial silicon-on-insulator (PSOI) technology for achieving high breakdown voltage and reduced power dissipation. In the proposed device, an N⁺ well is inserted in the buried oxide under the drain region. By optimizing the N⁺ well and the lateral distance between the buried oxide and the left side of the device, the electric field is modified. Therefore, the breakdown voltage improves. Also, the PSOI technology used in the proposed structure has a significant effect on reducing the lattice temperature. Our simulation results show that the proposed structure improves the breakdown voltage by about 67.5% and reduces the specific on-resistance by about 20% in comparison with a conventional LDMOS.