Ferroelectric-Gate Field Effect Transistors Using (Y,Yb)MnO3/Y2O3/Si(111) Structures for 1T-Type FeRAMs

Fabrication and characterization of metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFIS FETs) using (Y,Yb)MnO₃/Y₂O₃/Si structures were introduced for the first time. P-channel MFIS FETs were fabricated on n-type Si(111) substrates, in which an Y_0.5Yb_0.5MnO₃(200 nm)/Y₂O₃(25 nm) structure was used as gate insulator. The Y_0.5Yb_0.5MnO₃ and Y₂O₃ films were prepared by chemical solution deposition. A fabricated MFIS FETs showed the hysteresis loop due to spontaneous polarization in the I_D-V_GS characteristic, in which the memory window was about 0.9V when the applied gate voltage was swept between 8 V and ?8 V. Especially, the alternative drain current was retained after applying a single voltage pulse with a magnitude of +9 V or ?9 V.     

Inverse Capacitance-Voltage Characteristics of Bi3.25La0.75Ti3O12 Thin Film Pulsed Laser Deposited on Thermally Oxidized n-Type Si Substrates

Comparative studies on the electrical properties of a metal-ferroelectric-insulator-semiconductor field effect transistor were conducted using pulsed laser ablated ferroelectric Bi_3.25La_0.75Ti₃O₁₂ (BLT) thin films deposited on SiO₂/Si substrates with different SiO₂ thicknesses. The SiO₂ layer was prepared on n-type Si substrates by dry oxidation at a temperature of 800°C. Small angle x-ray reflectivity studies were used to measure the SiO₂ thickness. The capacitance-voltage (C-V) measurements revealed that the films showed good interfacial properties. Shifts in flatband voltages were observable, but were effectively reduced by deposition of the ferroelectric films. Au/BLT/SiO₂/Si diodes with 8 nm SiO₂ layer showed to be stable with relatively large memory window values of about 0.3 V, 2.5 V, 5.0 V, and 7.0 V, at increasing bias voltages of ±5 V, ±7 V, ±10 V, and ±12 V, respectively.     

Fabrication of amorphous bulk and multi-phase ceramics by melting method in the HfO2-Al2O3-Gd2O3-Eu2O3system

Ceramics have generally been fabricated from powders by shape forming & sintering methods except for glasses and glass ceramics. Glasses and glass ceramics can be fabricated by melting methods. The melting method has not only higher productivity but also higher shape forming ability than powder processes via forming & sintering methods. Thus we have reinvestigated melting methods in binary and ternary oxides systems to fabricate amorphous bulk ceramics and bulk nano composites. We have successfully fabricated amorphous phases by simple melt solidification methods in ternary eutectic melts in the HfO₂-Al₂O₃-Gd₂O₃system. The present study demonstrates the formation of the amorphous phases in quaternary systems HfO₂-Al₂O₃-Gd₂O₃-Eu₂O₃. Furthermore, we have also succeeded to fabricate nano-structured bulk ceramics, which consisted of constituent oxide grains with 20–100 nm in size, by post annealing of the amorphous phase.     

Phase Formations and Electrical Properties of Various (Bi, La)4Ti3O12 Thin Films by Chemical Solution Deposition

The phase formation and electrical properties of (Bi, La)₄Ti₃O₁₂ (BLT) thin film and V-, Sm-doped BLT thin films prepared by the chemical solution deposition method on Pt/TiO₂/SiO₂/Si substrates have been investigated. It was observed that the microstructure and electrical properties of BLT thin films dramatically varied with V- and Sm-doping. The crystallinity and grain size of BLT thin films were definitely increased by V- and Sm-doping into BLT films, which resulted in the enhancement of remanent polarization in doped BLT films. The remanent polarization (Pr) of Sm-doped BLT films annealed for 3 min by an RTA system was about 9 C/cm². The V- and Sm-doped BLT films also exhibited good fatigue characteristics under bipolar stressing to 10¹⁰ cycles.     

Electrical properties of ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructures

Ultrathin HfO₂ gate dielectrics have been deposited on strained Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. The polycrystalline HfO₂ film with a physical thickness of ∼6.5 nm and an amorphous interfacial layer with a physical thickness of ∼2.5 nm have been observed by high resolution transmission electron microscopy (HRTEM). The electrical properties have been studied using metal-oxide-semiconductor (MOS) structures. The fabricated MOS capacitors on Si_0.69 Ge_0.3C_0.01 show an equivalent oxide thickness (EOT) of 2.9 nm, with a low leakage current density of ∼4.5 × 10 ^{− 7} A/cm² at a gate voltage of –1.0 V. The fixed oxide charge and interface state densities are calculated to be 1.9 × 10¹² cm^{− 2} and 3.3 × 10 ¹¹ cm^{− 2}eV⁻¹, respectively. The temperature dependent gate leakage characteristics has been studied to establish the current transport mechanism in high-k HfO₂ gate dielectric to be Poole–Frenkel one. An improvement in electrical properties of HfO₂ gate dielectrics has been observed after post deposition annealing in O₂ and N₂ environments.     

Comparison of Hafnium Precursors for the MOCVD of HfO2 for Gate Dielectric Applications

Hafnium oxide films were deposited on Si (100) substrates using metal-organic chemical vapor deposition (MOCVD) and evaluated for gate dielectric applications. For this study, two types of precursors were tested: an oxygenated one, Hf butoxide-mmp, and an oxygen-free one, Hf diethyl-amide. Depositions were carried out in the temperature range of 350–650°C. However, the discussion is focused on amorphous films. The films were compared on the basis of growth rate, phase development, density, interface characteristics, and electrical properties. A similar amorphous to polycrystalline phase transition temperature was found for both precursors. For low deposition temperatures the growth rate for the amide precursor was significantly higher than for the butoxide-mmp precursor and films prepared with the amide precursor contained a lower carbon impurity content than with the butoxide-mmp one. The dielectric constant was slightly higher for amorphous HfO₂ deposited from the amide precursor than for the butoxide-mmp one. Only in respect to the trap density does the butoxide precursor seem advantageous.     

Ferroelectric Properties of (Bi, Sm)4Ti3O12 (BST) Thin Films Fabricated by a Metalorganic Solution Deposition Method

Ferroelectric properties of samarium substituted Bi₄Ti₃O₁₂ films, Bi_3.15Sm_0.85Ti₃O₁₂ (BST), were evaluated for use as lead-free thin film ferroelectrics for FeRAM applications. The BST films were fabricated on the Pt/Ti/SiO₂/Si(100) substrates by a metalorganic solution deposition method. The measured XRD patterns revealed that the BST films showed only a Bi₄Ti₃O₁₂-type phase with a random orientation. The BST film capacitors showed excellent ferroelectric properties. For the film capacitor annealed at 700C, 2P_r of 64.2 C/cm² and 2E_c of 101.7 kV/cm at applied electric field of 150 kV/cm were observed. The capacitor did not show any significant fatigue up to 1.5 × 10⁸ read/write switching cycles at a frequency of 1 MHz, which suggests that the samarium should be considered for a promising lanthanide elements to make a good thin ferroelectric film for memory applications.     

Asymmetric capacitance-voltage characteristics of (Bi3.25, La0.75)Ti3O12 thin films grown on Si

Abstract

Electrical properties of Lamodified bismuth titanate Bi_3.25La_0.75Ti₃O₁₂) thin films for a metal-ferroelectric-insulator-semiconductor (MFIS) structure were investigated with capacitance-voltage (C-V). The MFIS structure exhibits progressively increasing C-V memory window with a sweep voltage due to ferroelectric polarization with suppressed charge injection. Moreover, the asymmetric shift of threshold voltage with a sweep voltage was observed. The flat-band voltage (V_fb2) at the negative sweep was gradually increased with a sweep voltage. The flatband voltage (V_fb1) at the positive sweep decreased at low sweep voltages and then increased at further high voltages (i.e., V_fb1 shift toward the positive direction rather than the negative direction). The asymmetric behavior of C-V characteristics was attributed to negative trapped charges by electron injection from Si.     

Influence of B2O3/SiO2 Ratio on the Fabrication of Nd:YAG Ceramics

B₂O₃/SiO₂ are used as composite sintering aids to fabricate Nd:YAG ceramics by solid-state reaction and vacuum sintering method at 1750°C for 5h using Nano-Al₂O₃, Y₂O₃, Nd₂O₃ as starting materials. In this article, we focus on the influence of B₂O₃/SiO₂ ratio on grain size, porosity and relative density. Finally, with the increase of B₂O₃/SiO₂ ratio, the density and shrinkage rate of transparent ceramics increase, the grain size becomes uniform and the porosity reduces, for the reason that B³⁺ begins to vaporize at 1300°C and is reduced to trace levels by 1600°C. The best B₂O₃/SiO₂ ratio is 4: 1.     

Epitaxial structure SrBi2Ta2O9<116> /SrTiO3<011> /Ce0.12Zr0.88O2<001> /Si<001> for ferroelectric-gate FET memory

Abstract

Epitaxial thin film growth of SrBi₂Ta₂O₉/SrTiO₃/Ce_0.12Zr_0.88O₂ on Si was studied, and this epitaxial layer structure was applied to fabrication of ferroelectric-gate field effect transistors (FETs). The films were prepared by a pulsed laser deposition technique and epitaxial growth was identified by x-ray diffraction. The devices exhibited excellent electrical performances: Capacitance-voltage characteristic of a metal-ferroelectric-insulator-semiconductor (MFIS) diode showed a retention longer than 10 days and I_d-V_g characteristic of an MFIS-FET showed 1 day retention. It is proved that the crystalline quality of ferroelectric thin films is of great importance to develop integrated devices with high performance.     

Retention Characteristics of (Bi,La)4Ti3O12 Films on Si(100) Substrates Using LaAlO3 Buffer Layers

We demonstrate the ferroelectric behavior of (Bi,La)₄Ti₃O₁₂ (BLT) films deposited on Si(100) substrates by using LaAlO₃ buffer layers. LaAlO₃ films were prepared by molecular beam deposition method. Then, they were subjected to ex situ dry N₂ annealing in a rapid thermal annealing furnace. From the capacitance-voltage measurement, the dielectric constant of LaAlO₃ was estimated to be 20 to 26. On these structures, BLT films were deposited by sol-gel method and they were characterized by X-ray diffraction analysis. It was found from capacitance-voltage measurements that the characteristics showed a hysteresis loop and the memory window was about 0.5 V for the voltage sweep of ±9 V. It was also found from the retention measurement that the higher and lower capacitance values in the hysterisis loop could be distinguished at least for 3 days. It is concluded from these results that the BLT/LaAlO₃/Si(100) structure is one of the most promising structures for realizing MFISFETs (metal-ferroelectric-insulator-semiconductor field effect transistors).     

The Effect of La-Doped Bi4Ti3O12 Buffer Layer on Crystallinity and Ferroelectric Properties of PbZr0.58Ti0.42O3/Bi3.25La0.75Ti3O12 Multilayered Thin Films

PbZr_0.58Ti_0.42O₃ (PZT) ferroelectric thin films with Bi_3.25La_0.75Ti₃O₁₂ (BLT) buffer layer of various thickness were fabricated on Pt/TiO₂/SiO₂/p-Si(100) substrates by rf-magnetron sputtering method. The pure PZT film showed (111) preferential orientation in the XRD patterns, and the PZT/BLT films showed (110) preferential orientation with increasing thickness of the BLT layer. There were no obvious diffraction peaks for the BLT buffer layer, for its thin thickness in PZT/BLT multilayered films. There were the maximum number of largest-size grains in PZT/BLT(30 nm) film among all the samples from the surface images of FESEM. The growth direction and grain size had significant effects on ferroelectric properties of the multilayered films. The fatigue characteristics suggested that 30-nm-thick BLT was just an effective buffer layer enough to alleviate the accumulation of oxygen vacancies near the PZT/BLT interface. The comparison of these results suggests that the buffer layer with an appropriate thickness can improve the ferroelectric properties of multilayered films greatly.     

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices

Abstract

We have investigated the roles of buffer layer in the Pt/SBT-Y₂O₃/p-Si (MFIS) capacitors. We found that the insertion of Y₂O₃ buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However, negative charges with the effective density of 3.21×10¹²/cm² were generated due to the additional process step for Y₂O₃ deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y₂O₃ buffer layer minimize the charge injection, the shift of the hysteresis loops was asymmetrical.     

Formation of Silicate-Added (Bi,La)4Ti3O12 Films on LaAlO3/Si(100) Structures

We fabricated MFIS (metal-ferroelectric-insulator-semiconductor) diodes with ((Bi,La)₄Ti₃O₁₂: BLT) films and lanthanum silicate (La₂SiO₅: LSO)-added BLT films formed on LaAlO₃/Si(100) structures. LaAlO₃ films were prepared by an MBD (molecular beam deposition) method. After the film deposition, they were subjected to ex site N₂ annealing in a rapid thermal annealing (RTA) furnace at 800°C for 1 min. BLT films and LSO-added BLT films were deposited on these LaAlO₃/Si structures using a sol-gel technique. The memory windows of BLT and LSO-added BLT films were 3.0 V and 2.1 V, respectively. It was found from the current density-voltage (I-V) characteristics that the insulation property of the LSO-added BLT film was superior to that of the BLT film. We conclude from these results that LaAlO₃ is an excellent candidate of a buffer layer for forming ferroelectric-gate FETs and that the LSO-added BLT film is suitable for low voltage operation of the FETs.     

Characterization of the CeO2 thin films for insulation layer and Pt/SrBi2Ta2O9/CeO2/Si MFISFET structure

Abstract

CeO₂ and SrBi₂Ta₂O₉ (SBT) thin films for MFISFET (metal-fcrroelectrics-insulator-semiconductor field effect transistor) were deposited by rf sputtering and pulsed laser deposition method, respectively. The effects of oxygen partial pressure during deposition for CeO₂ films were investigated. The oxygen partial pressure significantly affected the preferred orientation, grain size and electrical properties of CeO₂ films. The CeO₂ thin films with a (200) preferred orientation were deposited on Si(100) substrates at 600°C. The films deposited under the oxygen partial pressure of 50 % showed the best C-V characteristics among those under various conditions. The leakage current density of films showed order of the 10^?7～10^?8 A/cm² at 100 kV/cm. The SBT thin films on CeO₂/Si substrate showed dense microstructure of polycrystalline phase. From the C-V characteristics of MFIS structure composed of the SBT film annealed at 800°C, the memory window width was 0.9 V at ±5 V. The leakage current density of Pt/SBT/CeO₂/Si structure annealed at 800°C was 4×10^?7 A/cm² at 5 V.     

Crystallization of Zr Based Oxide with Glass Forming Additives for Gate Dielectric Applications

In this study, Si, Al, and Bi have been investigated as a glass forming additive. Addition of glass forming materials is effective on stabilization of amorphous phase for Zr based films. The higher crystallization temperature results from the more additives. Addition of heavier atom is more effective on enhancing dielectric constant but results in lowering crystallization temperature. Addition of Si results in the most stable amorphous with significant reduction of dielectric constant. When the atomic ratio of Si over (Si + Zr) of about 0.55 is annealed at 950°C for 1 min, any crystallization behaviors are not noticed with dielectric constant of 12. On the other hand, addition of Al causes moderate improvement of crystallization behavior with small sacrifice of dielectric constant. The amorphous films of Zr_{1 ? x} Al _x O _y (X = 0.55) remain amorphous up to 800°C anneals with dielectric constant of 15.     

BaTiO 3 on YBa 2 Cu 3 O 7 High T C Superconductors-Microwave Properties

We have made both patterned and unpatterned BaTiO 3 on YBa 2 Cu 3 O 7 microwave test structures as well as identical YBa 2 Cu 3 O 7 test structures and characterized them at 3.3 and 35 GHz. In both cases we found that the best unloaded Q values of the test resonators was for devices made from BaTiO 3 coated YBa 2 Cu 3 O 7 . This had led us to conclude that, at low temperatures, BaTiO 3 does not add additional losses to the system and that it may, in addition to being a tunable ferroelectric material, aid in passivating the YBa 2 Cu 3 O 7 ' surface. We present here preparation and measurement details and discuss the direction of future work in this area.     

Ferroelectric properties of (Bi3.15 Nd 0.85 )Ti 3 O 12 with decreasing film thickness

Film texture and ferroelectric behaviors of (Bi_3.15Nd_0.85)Ti₃O₁₂ (BNdT) of layered-perovskite structure deposited on Pt/TiO₂/Si substrate are dependent on the film thickness. When the film thickness is reduced from ∼240 to ∼120 nm, BNdT grains evolve from a rod-like morphology to a spherical morphology, accompanied by a decrease in average grain size. At the same time, P-E hysteresis transforms from a square-shaped hysteresis loop (2Pr ∼24.1 μC/cm² at 240 nm) to a relative slimmer hysteresis loop (with a lower 2Pr = 19.8 μC/cm² at 120 nm). The nonvolatile polarization (Δ P) shows a maximum at the film thickness of 160 nm, where Δ P was measured to be 14.7 μC/cm² and 6.8 μC/cm² at 5 V and 3 V, respectively. A small amount of excess bismuth in the film thickness of 130 nm, introduced by co-sputtering, can lead to a much enhanced remanent polarization (2Pr of 21.3 μC/cm² at 5 V and 15.2 μC/cm²at 3 V), which is promising for low voltage FRAM applications.     

Current Conduction and Dielectric Behavior of High k-Y2O3 Films Integrated with Si Using Chemical Vapor Deposition as a Gate Dielectric for Metal-Oxide-Semiconductor Devices

Integration of Y₂O₃ high-k thin film over Si as gate dielectric in high performance CMOS and high-density MOS memory storage capacitor devices is described. Y₂O₃ film growth by low-pressure chemical vapor deposition induces interfacial reactions and complex SiO_{2 – x} layer growth. It has a graded structure, in crystalline-SiO₂ form at Y₂O₃ side and amorphous SiO_{2 – x} form at Si side. MIS devices based on Y₂O₃/SiO₂-SiO_{2 – x} composite dielectric integrated with Si show high frequency C-V behavior indicative of inversion to accumulation changes in capacitance. Observed bi-directional hysterisis in C-V is detrimental to the functioning of storage capacitor in memory function. Detailed investigation of this effect led to understanding of gate bias controlled emission of carriers as responsible mechanism. Observed anomalous increase in inversion capacitance at low frequency is attributed to additional charges transferred from SiO_{2 – x}/Si interface states. Leakage current and injected charge carrier transport across bilayer interface is dominated by Poole-Frankel (PF) process at low fields and by Fowler-Nordhiem (FN) at high fields. This investigation provides a greater understanding of the complex nature of integration of Y₂O₃ films.     

Crystal Growth and Dielectric Properties of New Ferroelectric Barium Titanate: BaTi2O5

Single crystals of the ferroelectric BaTi₂O₅ and BaTiO₃ were prepared from a solution of 33-mol% BaO and 67-mol% TiO₂ by a rapid cooling method. The dielectric constant () and dielectric loss tangent (tan) were measured in a wide temperature range of 10–860 K and in a frequency range of 0.1–3,000 kHz. The along the b-axis of the BaTi₂O₅ crystal, prepared in air, shows a sharp dielectric anomaly reaching 30,000 at the ferroelectric Curie temperature of T_C = 752 K. By contrast, the crystal prepared in a reducing atmosphere shows a diffuse phase transition near T_C = 703 K. The values of and tan are compared between these three crystals consisting of two kinds of BaTi₂O₅ and one BaTiO₃.