Effects of Ar post-annealing on the electrical properties of Pt/YMnO3/p-Si and Pt/YMnO3/Y2O3/p-Si

Abstract

YMnO₃ thin films were prepared on p-Si(111) and Y₂O₃/p-Si(111) substrates by chemical solution deposition and annealed at 800°C for 1 hour under the oxygen pressure of 2 Torr. The YMnO₃ thin films showed good crystallinity and c-axis preferred orientation. Effects of Ar post-annealing on electrical properties were examined in Pt/YMnO₃/p-Si and Pt/YMnO₃/Y₂O₃/p-Si structures. Leakage current densities decreased considerably by Ar post-annealing. The Pt/YMnO₃/p-Si and Pt/YMnO₃/Y₂O₃/p-Si showed clockwise C-V hysteresis induced by ferroelectric polarization after Ar post-annealing and memory windows of MFS and MFIS structure were 1.1V and 0.6V, respectively.     

Asymmetric capacitance-voltage characteristics of (Bi3.25, La0.75)Ti3O12 thin films grown on Si

Abstract

Electrical properties of Lamodified bismuth titanate Bi_3.25La_0.75Ti₃O₁₂) thin films for a metal-ferroelectric-insulator-semiconductor (MFIS) structure were investigated with capacitance-voltage (C-V). The MFIS structure exhibits progressively increasing C-V memory window with a sweep voltage due to ferroelectric polarization with suppressed charge injection. Moreover, the asymmetric shift of threshold voltage with a sweep voltage was observed. The flat-band voltage (V_fb2) at the negative sweep was gradually increased with a sweep voltage. The flatband voltage (V_fb1) at the positive sweep decreased at low sweep voltages and then increased at further high voltages (i.e., V_fb1 shift toward the positive direction rather than the negative direction). The asymmetric behavior of C-V characteristics was attributed to negative trapped charges by electron injection from Si.     

Fabrication of MFIS diodes using sol-gel derived SBT films and LaAlO3 buffer layers

Abstract

We demonstrate the ferroelectric behavior of Sr_0.8Bi_2.2Ta₂O₉ (SBT) films grown on Si(100) substrates by using lanthanum aluminate (LaAlO₃) buffer layers. LaAlO₃ films were prepared by vacuum evaporation method. Then, they were subjected to ex situ dry N₂ annealing in a rapid thermal annealing (RTA) furnace. From the capacitance-voltage (C-V) measurement, the dielectric constant of LaAlO₃ was estimated to be 20～25. On these substrates, SBT films (210nm) were deposited by sol-gel method and they were characterized by XRD analysis after annealing under various conditions. It was found from C-V characteristics that the memory window of an SBT film annealed at 750°C for 30min in O₂ atmosphere was about 3.0V for the voltage sweep of ±10V. It was also found from the retention measurement that the capacitance values of the SBT film annealed at 750°C did not change over 12hours. It is concluded from these results that the SBT/LaAlO₃/Si(100) structure is one of the most promising structures for realizing MFISFETs (metal-ferroelectric-insulator-semiconductor field-effect-transistors).     

Characterization of the CeO2 thin films for insulation layer and Pt/SrBi2Ta2O9/CeO2/Si MFISFET structure

Abstract

CeO₂ and SrBi₂Ta₂O₉ (SBT) thin films for MFISFET (metal-fcrroelectrics-insulator-semiconductor field effect transistor) were deposited by rf sputtering and pulsed laser deposition method, respectively. The effects of oxygen partial pressure during deposition for CeO₂ films were investigated. The oxygen partial pressure significantly affected the preferred orientation, grain size and electrical properties of CeO₂ films. The CeO₂ thin films with a (200) preferred orientation were deposited on Si(100) substrates at 600°C. The films deposited under the oxygen partial pressure of 50 % showed the best C-V characteristics among those under various conditions. The leakage current density of films showed order of the 10^?7～10^?8 A/cm² at 100 kV/cm. The SBT thin films on CeO₂/Si substrate showed dense microstructure of polycrystalline phase. From the C-V characteristics of MFIS structure composed of the SBT film annealed at 800°C, the memory window width was 0.9 V at ±5 V. The leakage current density of Pt/SBT/CeO₂/Si structure annealed at 800°C was 4×10^?7 A/cm² at 5 V.     

Ferroelectric-Gate Field Effect Transistors Using (Y,Yb)MnO3/Y2O3/Si(111) Structures for 1T-Type FeRAMs

Fabrication and characterization of metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFIS FETs) using (Y,Yb)MnO₃/Y₂O₃/Si structures were introduced for the first time. P-channel MFIS FETs were fabricated on n-type Si(111) substrates, in which an Y_0.5Yb_0.5MnO₃(200 nm)/Y₂O₃(25 nm) structure was used as gate insulator. The Y_0.5Yb_0.5MnO₃ and Y₂O₃ films were prepared by chemical solution deposition. A fabricated MFIS FETs showed the hysteresis loop due to spontaneous polarization in the I_D-V_GS characteristic, in which the memory window was about 0.9V when the applied gate voltage was swept between 8 V and ?8 V. Especially, the alternative drain current was retained after applying a single voltage pulse with a magnitude of +9 V or ?9 V.     

Low-temperature synthesis in vacuum of c-axis oriented ferroelectric YMnO3 thin films using alkoxy-derived precursors

Abstract

Hexagonal YMnO₃ thin films were prepared on Pt(111)/TiO_x/SiO₂/Si and Pt(111)/Al₂O₃(0001) substrates using alkoxy-derived precursor solutions. The films were prepared by spin coating the YMnO₃ precursor solutions and then, the films were calcined and crystallized via rapid thermal annealing in oxygen or vacuum ambient. The annealing conditions and substrates were critical for crystallization of ferroelectric YMnO₃ films. When annealed in vacuum, the films both on Pt(111)/TiO_x/SiO₂/Si and Pt(111)/Al₂O₃(0001) substrates crystallized to hexagonal YMnO₃ and the orientation depended on the substrates. The film on Pt(111)/Al₂O₃(0001) had c-axis orientation and the film on Pt(111)/TiO_x/SiO₂/Si had no preferred orientation. In addition, it was found that crystallization behavior, orientation and morphology of YMnO₃ films on Pt(111)/TiO_x/SiO₂/Si substrates depended on the annealing condition. The heat-treatment in vacuum at initial stage for crystallization affected the restraint of perovskite phase and formation of hexagonal phase. The following heat-treatment in oxygen promoted the c-axis orientation and grain growth. The optimum annealing procedure for crystallization of the c-axis oriented YMnO₃ films on Pt(111)/TiO_x/SiO₂/Si was addressed.     

CHARACTERISTICS OF METAL-FERROELECTRIC-INSULATOR-SILICON DEVICES USING HFSION BUFFER LAYERS

ABSTRACT

In this work, metal-ferroelectric-insulator-silicon (MFIS) devices were fabricated using HfSiON as buffer layers and their electrical properties were studied. Ultra-thin HfSiON films were fabricated by electron-beam evaporation at room temperature and post-annealed using different parameters such as temperature, time in O₂. By annealing a 2 nm-thick HfSiON film at 800°C for 60s in O₂, a negligible hysteresis loop and small equivalent oxide thickness of 2.3 nm were obtained with a corresponding leakage current density of 6.8 × 10^{? 5} A/cm² at a voltage shifted from the flat band voltage by 1 V. In the fabrication of MFIS diodes, Sr_0.8Bi_2.2Ta₂O₉ (SBT) films with 400 nm thickness were formed by chemical solution deposition. For Pt/SBT (400 nm)/HfSiON(2 nm)/Si diodes, a memory window of 0.8 V in width was observed during double capacitance-voltage sweep between +5 and –5 V. At the same time, excellent data retention properties were observed. The high and low capacitances in the hysteresis loop were well distinguishable even after 24 h had elapsed.     

Laser ablation preparation and property of bismuth-layer-structured SrBi2Ta2Ta2O9 and Bi4Ti3O12 ferroelectric thin films

Abstract

Bismuth-layer-structured ferroelectric thin films, SrBi₂Ta₂O₉ and Bi₄Ti₃O₁₂, have been prepared by laser ablation method on both Pt sheets and Si wafers at low temperatures of 400 ～ 500°C. These thin films have been characterized by XRD, XPS, AFM, C-V, D-E hysteresis and J-V measurement. SrBi₂Ta₂O₉ thin films have a good (105) preferential orientation, and Bi₄Ti₃O₁₂ thin films have (117) and c-axis orientation on these substrates. Ferroelectric film-SiO₂-Si structures show good C-V hysteresis curve owing to Si surface potential controlled by the D-E hysteresis. D-E hysteresis is obtained in Bi₄Ti₃O₁₂ thin film prepared on Pt sheet, and the remnant polarization and the coercive force are 7.5 μC/cm² and 72 kV/cm, respectively.     

Inverse Capacitance-Voltage Characteristics of Bi3.25La0.75Ti3O12 Thin Film Pulsed Laser Deposited on Thermally Oxidized n-Type Si Substrates

Comparative studies on the electrical properties of a metal-ferroelectric-insulator-semiconductor field effect transistor were conducted using pulsed laser ablated ferroelectric Bi_3.25La_0.75Ti₃O₁₂ (BLT) thin films deposited on SiO₂/Si substrates with different SiO₂ thicknesses. The SiO₂ layer was prepared on n-type Si substrates by dry oxidation at a temperature of 800°C. Small angle x-ray reflectivity studies were used to measure the SiO₂ thickness. The capacitance-voltage (C-V) measurements revealed that the films showed good interfacial properties. Shifts in flatband voltages were observable, but were effectively reduced by deposition of the ferroelectric films. Au/BLT/SiO₂/Si diodes with 8 nm SiO₂ layer showed to be stable with relatively large memory window values of about 0.3 V, 2.5 V, 5.0 V, and 7.0 V, at increasing bias voltages of ±5 V, ±7 V, ±10 V, and ±12 V, respectively.     

Current Conduction and Dielectric Behavior of High k-Y2O3 Films Integrated with Si Using Chemical Vapor Deposition as a Gate Dielectric for Metal-Oxide-Semiconductor Devices

Integration of Y₂O₃ high-k thin film over Si as gate dielectric in high performance CMOS and high-density MOS memory storage capacitor devices is described. Y₂O₃ film growth by low-pressure chemical vapor deposition induces interfacial reactions and complex SiO_{2 – x} layer growth. It has a graded structure, in crystalline-SiO₂ form at Y₂O₃ side and amorphous SiO_{2 – x} form at Si side. MIS devices based on Y₂O₃/SiO₂-SiO_{2 – x} composite dielectric integrated with Si show high frequency C-V behavior indicative of inversion to accumulation changes in capacitance. Observed bi-directional hysterisis in C-V is detrimental to the functioning of storage capacitor in memory function. Detailed investigation of this effect led to understanding of gate bias controlled emission of carriers as responsible mechanism. Observed anomalous increase in inversion capacitance at low frequency is attributed to additional charges transferred from SiO_{2 – x}/Si interface states. Leakage current and injected charge carrier transport across bilayer interface is dominated by Poole-Frankel (PF) process at low fields and by Fowler-Nordhiem (FN) at high fields. This investigation provides a greater understanding of the complex nature of integration of Y₂O₃ films.     

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices

Abstract

We have investigated the roles of buffer layer in the Pt/SBT-Y₂O₃/p-Si (MFIS) capacitors. We found that the insertion of Y₂O₃ buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However, negative charges with the effective density of 3.21×10¹²/cm² were generated due to the additional process step for Y₂O₃ deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y₂O₃ buffer layer minimize the charge injection, the shift of the hysteresis loops was asymmetrical.     

C-Axis Oriented MOCVD YMnO3 Thin Film and Its Electrical Characteristics in MFIS FeTRAM

Yttrium manganate (YMO) thin films were prepared on SiO₂ buffered silicon as a candidate for ferroelectric transistor random access memory (FeTRAM). The films were deposited by flash evaporated MOCVD at low temperature and post annealed to crystallize the c-axis oriented hexagonal YMO phase. It is found that oxygen content and substrate temperature are major parameters determining c-axis orientation. For the electrical characteristics, P_r (remnant polarization) ～2 μ C/cm² and ? (dielectric constant) ～ 20 are obtained in Pt/YMO/Pt structures. It is also found that a top buffer layer of 30 nm ZrO₂ helps to reduce the leakage current of Pt/top buffer/YMO/SiO₂/Si stack to 10^{? 7} A/cm² and improves the C-V memory window from 0.2 V to 2 V.     

Retention Characteristics of (Bi,La)4Ti3O12 Films on Si(100) Substrates Using LaAlO3 Buffer Layers

We demonstrate the ferroelectric behavior of (Bi,La)₄Ti₃O₁₂ (BLT) films deposited on Si(100) substrates by using LaAlO₃ buffer layers. LaAlO₃ films were prepared by molecular beam deposition method. Then, they were subjected to ex situ dry N₂ annealing in a rapid thermal annealing furnace. From the capacitance-voltage measurement, the dielectric constant of LaAlO₃ was estimated to be 20 to 26. On these structures, BLT films were deposited by sol-gel method and they were characterized by X-ray diffraction analysis. It was found from capacitance-voltage measurements that the characteristics showed a hysteresis loop and the memory window was about 0.5 V for the voltage sweep of ±9 V. It was also found from the retention measurement that the higher and lower capacitance values in the hysterisis loop could be distinguished at least for 3 days. It is concluded from these results that the BLT/LaAlO₃/Si(100) structure is one of the most promising structures for realizing MFISFETs (metal-ferroelectric-insulator-semiconductor field effect transistors).     

MFIS and MFMIS structures using Pb(Zr,Ti)O3 films for nonvolatile memory devices

Abstract

In this work, metal / ferroelectric / insulator / semiconductor (MFIS) and metal / ferroelectric / metal / insulator / semiconductor (MFMIS) structures using Pb(Zr, Ti)O₃ (PZT) films were fabricated and characterized for nonvolatile NDRO memory device. 300nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO₄(ZT)/Si and Pt/ZT/Si substrates. C-V hysteresis were measured in both MFIS and MFMIS structures. By using a small-size MFM capacitor on a large-size MIS structure, it was found that the memory window of MFMIS structure was larger than that of the MFIS structure. There is a critical area ratio (S_MIS/S_MFM) in MFMIS structure. When an area ratio in MFMIS structure is below 12, the memory window increased with increasing area ratio. We could obtain that the memory window of MFMIS structure with a S_MIS/S_MFM of 11.8 was 2.1 V and 3.2 V with an applied voltage at 3 V and 5 V.     

Low temperature preparation of ferroelectric SrBi2Ta2O9 thin films by a modified RF magnetron sputtering technique

Abstract

Bi–layered ferroelectric SrBi₂Ta₂O₉ (SBT) films were successfully prepared on Pt/Ti/SiO₂/Si substrates at 650°C by a modified rf magnetron sputtering technique. The SBT films annealed for 1 h in O₂ (760 torr) and again for 30 min in O₂ (5 torr) at 650°C show a average grain size of about 49 nm. The SBT films annealed at 65 0°C have a remanent polarization (P_r) of 6.0 μC/cm² and coercive field (E_c) of 36 kV/cm at an excitation voltage of 5 V. The films showed fatigue–free characteristics up to 4.0 × 10¹⁰ switching cycles under 5 V bipolar pulse. The retention characteristics of SBT films looked very promosing up to 1.0 × 10⁵ s.     

Synthesis and properties of ferroelectric Si-doped (Bi, Nd)4Ti3O12 thin films by chemical solution deposition

Ferroelectric Si-doped (Bi,Nd)₄Ti₃O₁₂ thin films have been prepared on Pt/TiO_x/SiO₂/Si substrates through metal-organic compounds by the chemical solution deposition. The Bi_3.25Nd_0.75Ti_2.9Si_0.1O₁₂ (BNTS) precursor films were found to crystallize into the Bi-layered perovskite Bi₄Ti₃O₁₂ single-phase above 600^∘C. The synthesized BNTS films revealed a random orientation having a strong 117 reflection. The BNTS thin films prepared between 600^∘C and 700^∘C showed well-saturated P-E hysteresis loops with P _r of 13–14 μ C/cm² and E _c of 100–110 kV/cm at an applied voltage of 5 V. The surface roughness of the BNTS thin films was improved by Si doping compared with that of undoped Bi_3.35Nd_0.75Ti₃O₁₂ films.     

Properties of Chemical Solution Deposited Polycrystalline Neodymium-Modified Bi4Ti3O12

Thin films of neodymium-modified bismuth titanate Bi_3.44Nd_0.56Ti₃O₁₂ (BNT) were grown on Pt/TiO₂/SiO₂/Si substrates using chemical solution deposition method. The capacitors made by applying top Au electrodes on BNT films showed significantly improved values of the remanent polarization as compared to that using bismuth titanate Bi₄Ti₃O₁₂ (BT) films. The 2P _r value for the BNT capacitors was determined to be equal to 38 C/cm² at an applied voltage of 24 V, whereas, for Bi₄Ti₃O₁₂ (BT) capacitors a value of 20 C/cm² was measured at the same applied voltage. The maximum piezoelectric and pyroelectric coefficients of 22 pm/V and 112 C/m² K respectively, were measured for the BNT thin films.     

Effects of nitridation treatments for SBT/Ta2O5 stack gate capacitors

Abstract

In this study, effects of ICP nitride treatments on characteristics of ferroelectric gate stack capacitor were investigated for FET type ferroelectric memory applications. Pt/SBT(200nm)/Ta₂O₅(20nm)/ Nitride/Si (MeFINS) structure capacitors show wide ΔV (memory window) of 1.06V under ±3V operation, while Pt/SBT(200nm)/ Ta2O₅(20nm)/Si (MeFIS) capacitors without nitride treatments exhibit memory window of 0.60V. At the same time, an accumulation capacitance of the MeFINS structure device is higher than that of the MeFIS structure capacitor. This result implies that the ICP nitride treatment successfully suppresses a formation of low dielectric constant interfacial SiO_x layer and alleviates a series capacitance problem.     

The role of buffer layer in strontium bismuth tantalate based ferroelectric gate mos structures for non-volatile non destructive read out memory applications

Abstract

Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO₂) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO₂ film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.     

BaMgF4 thin film development and processing for ferroelectric FETS

Abstract

A ferroelectric memory field-effect transistor (FEMFET) where a ferroelectric thin film is incorporated directly into the gate structure of the transistor is attractive, because it provides not only nonvolatility, but also nondestructive readout (NDRO). At Westinghouse, we are currently developing a FEMFET using thin film barium magnesium fluoride (BaMgF₄), a ferroelectric material that was discovered in 1969, but was not fabricated in thin film form until 1989. The BaMgF₄ films are grown by evaporation in an ultrahigh vacuum (UHV) chamber on clean Si(100). The natural tendency of these films to grow with the ferroelectric a-axis in the Si(100) plane has been overcome to obtain more random orientation with larger reversible polarization perpendicular to the film. A capping layer (SiO₂) has been found to be essential for process integrability of these BaMgF₄ films. Ti-W metallization produced only a slight reduction in the capacitance-voltage (C-V) memory window. Switching speed of these films has been measured to be 40 to 45 nanoseconds. The first FEMFET fabricated with BaMgF₄ has exhibited 18 Volt memory hysteresis window with better than 10⁵ on/off current ratio for 20 Volt programming.