Investigation on various insulator layers for MFIS capacitors

Abstract

Effects of insulator layers of Metal(Au)/Ferroelectrics(PZT)/Insulator/Si (MFIS) structure capacitors are investigated for non-destructive type non-volatile memory device applications. Various high dielectric oxide layers such as Al₂O₃, Ta₂O₅, TiO₂ and ZrO₂ were fabricated by reactive sputtering as insulating layers. The oxide insulators give significant impacts on the morphologies of PZT layer and the properties of capacitors. It is noted that the oxide layers with small thermal expansions (<6x10^–6/°C) coefficient caused cracks on PZT films during PZT crystallization annealing. The effects of insulators as a diffusion barrier are also comparatively studied using Auger electron spectroscopy. In addition, the characteristics of high dielectric solid solution, such as titanium oxide-zirconium oxide, are also studied.     

The Effects of Integration Processes on Properties of One Transistor MFMPOS Memory Devices

Integration processing of one-transistor memory devices deals with the following issues: film quality of ferroelectric materials, integration process induced damages such as etching and forming gas annealing damage of ferroelectric materials, the alignment for devices. In order to make high quality one-transistor memory devices, integration processes including nitride gate replacement, oxide trench etching structures, selective deposition, etc. have been investigated for fabrication of one transistor MFMPOS (M: Metal, F: Ferroelectrics, M: Metal, P: polysilicon, O: oxide, S: silicon) memory devices. The integration processes for one transistor memory device have also been optimized to reduce process-induced damages. Based on the experimental results, MOCVD selective deposition can make higher quality patterned ferroelectric thin films, damascene structure with CMP processes can reduce the etching damages. Therefore, the high quality one transistor MFMPOS memory devices have been made.     

MFIS and MFMIS structures using Pb(Zr,Ti)O3 films for nonvolatile memory devices

Abstract

In this work, metal / ferroelectric / insulator / semiconductor (MFIS) and metal / ferroelectric / metal / insulator / semiconductor (MFMIS) structures using Pb(Zr, Ti)O₃ (PZT) films were fabricated and characterized for nonvolatile NDRO memory device. 300nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO₄(ZT)/Si and Pt/ZT/Si substrates. C-V hysteresis were measured in both MFIS and MFMIS structures. By using a small-size MFM capacitor on a large-size MIS structure, it was found that the memory window of MFMIS structure was larger than that of the MFIS structure. There is a critical area ratio (S_MIS/S_MFM) in MFMIS structure. When an area ratio in MFMIS structure is below 12, the memory window increased with increasing area ratio. We could obtain that the memory window of MFMIS structure with a S_MIS/S_MFM of 11.8 was 2.1 V and 3.2 V with an applied voltage at 3 V and 5 V.     

Recent progress of FET-type ferroelectric memories

Abstract

Recent progress of FET-type ferroelectric memories is reviewed. It is described that insersion of a buffer layer between the ferroelectric film and Si substrate is essential in preventing interdiffusion of the constituent elements. It is also shown, however, that existence of the buffer layer degrades the data retention characteristic severely. Necessary conditions to solve the short retention time problem are discussed, paying particular attention to comparison of MFIS (metal-ferroelectric-insulator-semiconductor) and MFMIS structures. Finally, a novel ferroelectric-gate FET is proposed, in which the depolarization field is expected not to be generated in the ferroelectric film.     

Reduction of Leakage Current by HfO 2 High K Dielectric Film Stacked on the Ferroelectric Layer of a MFIS Structure

We report here the reduction of leakage current through a thin ferroelectric layer by insertion of an HfO 2 film. We fabricated metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) and metal-ferroelectric-insulator-metal (MFIS) structures. A Pb x La 1 m x TiO 3 (PLT) ferroelectric layer was deposited on a thermally oxidized p-type Si substrate with a Zr buffer layer. Adopting an HfO 2 layer on the ferroelectric layer of a MIFIS structure with an equivalent oxide thickness (EOT) of 5 nm resulted in a reduction by only 13 percent of the voltage distribution on the ferroelectric layer. Applying HfO 2 to the ferroelectric layer of a MFIS structure, however, led to a 70% decrease in leakage current: from 2.7 2 10 m 8 to 0.76 2 10 m 8 A/cm 2 at +1 V. An HfO 2 film, by itself, shows leakage that is 3 orders of magnitude smaller than that of PLT; clearly, insertion of the film impedes leakage through the ferroelectric layer. This characteristic is believed to contribute to extension of the retention time of MFMIS FETs.     

The role of buffer layer in strontium bismuth tantalate based ferroelectric gate mos structures for non-volatile non destructive read out memory applications

Abstract

Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO₂) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO₂ film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.     

Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices

We present a hierarchy of tunneling models suitable for the two- and three-dimensional simulation of logic and nonvolatile semiconductor memory devices. The crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and nonvolatile memory devices.     

CHARACTERISTICS OF METAL-FERROELECTRIC-INSULATOR-SILICON DEVICES USING HFSION BUFFER LAYERS

ABSTRACT

In this work, metal-ferroelectric-insulator-silicon (MFIS) devices were fabricated using HfSiON as buffer layers and their electrical properties were studied. Ultra-thin HfSiON films were fabricated by electron-beam evaporation at room temperature and post-annealed using different parameters such as temperature, time in O₂. By annealing a 2 nm-thick HfSiON film at 800°C for 60s in O₂, a negligible hysteresis loop and small equivalent oxide thickness of 2.3 nm were obtained with a corresponding leakage current density of 6.8 × 10^{? 5} A/cm² at a voltage shifted from the flat band voltage by 1 V. In the fabrication of MFIS diodes, Sr_0.8Bi_2.2Ta₂O₉ (SBT) films with 400 nm thickness were formed by chemical solution deposition. For Pt/SBT (400 nm)/HfSiON(2 nm)/Si diodes, a memory window of 0.8 V in width was observed during double capacitance-voltage sweep between +5 and –5 V. At the same time, excellent data retention properties were observed. The high and low capacitances in the hysteresis loop were well distinguishable even after 24 h had elapsed.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Asymmetric capacitance-voltage characteristics of (Bi3.25, La0.75)Ti3O12 thin films grown on Si

Abstract

Electrical properties of Lamodified bismuth titanate Bi_3.25La_0.75Ti₃O₁₂) thin films for a metal-ferroelectric-insulator-semiconductor (MFIS) structure were investigated with capacitance-voltage (C-V). The MFIS structure exhibits progressively increasing C-V memory window with a sweep voltage due to ferroelectric polarization with suppressed charge injection. Moreover, the asymmetric shift of threshold voltage with a sweep voltage was observed. The flat-band voltage (V_fb2) at the negative sweep was gradually increased with a sweep voltage. The flatband voltage (V_fb1) at the positive sweep decreased at low sweep voltages and then increased at further high voltages (i.e., V_fb1 shift toward the positive direction rather than the negative direction). The asymmetric behavior of C-V characteristics was attributed to negative trapped charges by electron injection from Si.     

Enhanced SiO/sub 2/ reliability on deuterium-implanted silicon

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO/sub 2/ and Si/SiO/sub 2/ interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy.     

Ferroelectric Pb5Ge3O11 MFMOS capacitor for one transistor memory applications

Abstract

The basic mechanism for an one transistor memory device has been studied. Many ferroelectric materials such PbZr_xTi_1?xO₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁ (PGO) etc. were analyzed for this application. Because of its low remanent polarization and low dielectric constant, the c-oriented Pb₅Ge₃O₁₁ thin film was selected for one-transistor memory applications. Pb₅Ge₃O₁₁ thin films have been prepared using MOCVD and RTP (Rapid Thermal Process) post-annealing. Lead bis-tetramethylheptadione [Pb(thd)₂] and germanium ethoxide [Ge(OC₂H₅)₄] were used as the precursors. The Pb₅Ge₃O₁₁thin films were deposited onto Ir/Ti/SiO₂/Si wafers to measure their compositions, phase formation, microstructure and ferroelectric properties. The extremely highly c-oriented Pb₅Ge₃O₁₁ thin films showed good ferroelectric and electrical properties. A 300 nm thick PGO thin film exhibited a square and saturated hysteresis loop with 2Pr of 3.98 μC/cm², 2Ec of 128 KV/cm at an applied voltage 5V, leakage current of 5.1×10^?7 A/cm² at 100 KV/cm, and dielectric constant of close to 36. The c-axis oriented Pb₅Ge₃O₁₁ thin film also exhibited very good retention properties. The experimental results showed that a Pb₅Ge₃O₁₁ MFMOS gate stack is suitable for one-transistor memory applications.     

Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.     

Dielectric strength of series connected vacuum gaps

A simple procedure to obtain an analytical equation for the distribution function of breakdown voltage in devices containing an arbitrary number of identical elements in series is proposed. The obtained results make possible to analyze an influence of static properties of the elements and their number on the dielectric strength of a device as a whole. The probability of the breakdown of the switching device is calculated using the empirical distribution functions of breakdown voltages of each TVS. The Weibull plots are used to analyze the breakdown test results. The measurement of the dielectric strength performed for AC and DC devices shows a good agreement with the calculated data.     

SiC MOSFET与SiC SBD换流单元瞬态模型

相较于硅(Si)器件,碳化硅(SiC)器件所具有的高开关速度与低通态电阻特性增加了其瞬态波形的非理想特性与对杂散参数影响的敏感性,对其瞬态建模的精度提出更高的要求。通过功率开关器件瞬态过程的时间分段、机理解耦与参数解耦,突出器件开关特性,弱化物理机理,简化瞬态过程分析,建立基于SiC MOSFET与SiC SBD的换流单元瞬态模型。理论计算结果与实验结果对比表明,该模型能够较为精细地体现SiC MOSFET开关瞬态波形且能够较为准确地计算SiC MOSFET开关损耗。该模型参数可全部由数据手册提取,有较强的实用性。     

Effects of electrical leakage currents on MEMS reliability and performance

Electrostatically driven MEMS devices commonly operate with electric fields as high at 10/sup 8/ V/m applied across the dielectric between electrodes. Even with the best mechanical design, the electrical design of these devices has a large impact both on performance (e.g., speed and stability) and on reliability (e.g., corrosion and dielectric or gas breakdown). In this paper, we discuss the reliability and performance implications of leakage currents in the bulk and on the surface of the dielectric insulating the drive (or sense) electrodes from one another. Anodic oxidation of poly-silicon electrodes can occur very rapidly in samples that are not hermetically packaged. The accelerating factors are presented along with an efficient early-warning scheme. The relationship between leakage currents and the accumulation of quasistatic charge in dielectrics are discussed, along with several techniques to mitigate charging and the associated drift in electrostatically actuated or sensed MEMS devices. Two key parameters are shown to be the electrode geometry and the conductivity of the dielectric. Electrical breakdown in submicron gaps is presented as a function of packaging gas and electrode spacing. We discuss the tradeoffs involved in choosing gap geometries and dielectric properties that balance performance and reliability.     

Iridium thin film as a bottom electrode for high dielectric (Ba,Sr)TiO3 capacitors

Abstract

We propose Ir thin films as new electrode materials for high dielectric BST capacitors. Ir was found to be superior to Pt in a number of aspects such as resistivity, adhesion and surface roughness. The Pt/BST/Ir/SiO₂/Si capacitors showed leakage currents as low as Pt/BST/Pt/SiO₂/Si ones, but higher capacitance resulted. For endurance properties with +5V unipolar pulse trains, the dielectric constant of BST films on Ir decreased by only 10% below its initial value after switching of 10⁹ cycles while that on Pt degraded by 30% after 10⁸ cycles. Ir bottom electrode effects on BST film properties were well explained by the formation of IrO₂ phases on the surface of Ir electrodes.     

Current status of resistive nonvolatile memories

Several emerging nonvolatile memories (NVMs) such as ferroelectric memory, magnetoresistive rams and ovonic universal memory are being developed for possible applications. Resistive random access memory (RRAM) is another interesting competitor in the class of NVMs. The RRAM is based on a large change in electrical resistance when the memory film is exposed to voltage or current pulses, and can keep high or low resistance states without any power. The ideal RRAM should have the superior properties of reversible switching, long retention time, multilevel switching, simple structure, small size, and low operating voltage. Perovskite oxides, transition metal oxides, and molecular materials were found to have resistive memory properties. This presentation reviews the ongoing research and development activities on future resistance NVMs technologies incorporating these new memory materials. The possible basic mechanisms for their bistable resistance switching are described. The effect of processing, composition, and structure on the properties of resistive memory materials and consequently the devices are discussed.     

Low-Temperature Process of Ferroelectric (Y0.95,Bi0.05)MnO3 Thin Films and Their Structural and Electrical Properties

[(Y_0.95,Bi_0.05)MnO₃] (YBM) films have been grown on Y₂O₃ buffered Si (001) by pulsed-laser deposition (PLD). We have compared the structural and dielectric properties of YBM films with those of typical YMnO₃ films from the viewpoint of lowering the process temperature. The highly c-axis oriented YBM film have been obtained on Y₂O₃/Si (001) at 700°C, which is a significantly reduced growth temperature from that of typical YMnO₃ films (850°C). The Bi modification was effective for the low temperature processing of YBM films. These highly c-axis oriented YBM films was obtained only at high ambient oxygen pressures, for example above 100 mTorr, contrary to YMnO₃ films which requires low ambient oxygen pressure for the growth of c-axis preferred orientation. The dielectric constant and dissipation factor was 29 and 0.017 at 1 MHz, respectively. The memory window due to ferroelectric polarization switching was found in a capacitance-voltage (C-V) characteristic. The YBM/Y₂O₃/Si structure with above characteristics of YBM films exhibited the C-V memory window of 1.2 V at a sweep voltage of 5 V. The flat-band voltage shifted symmetrically with increasing the sweep voltage up to 8 V due to little charge injection from Si. As a result, the memory window increased progressively with increasing the sweep voltage and amounted to 2 V at a sweep voltage of 8 V. The leakage current density was below 5 × 10^?7 A/cm² at a bias voltage of 8 V.     

Integration and characterization of MFISFET using Pb5Ge3O11

Abstract

The first MFIS FETs PMOS using Pt/Pb₅Ge₃O₁₁/ZrO₂/n-Si structure has been successfully fabricated. The PGO thin film was deposited by spin on method. Single phase PGO with strong c-axis orientation and low leakage current was obtained on ZrO₂ substrate. Pt was used as top electrode and the gate stack was dry etched using chlorine chemistry. Using CMOS compatible process, the integration of MFIS FETs is simple and reliable. I_D-V_G and I_D-V_D were characterized on 10 × 10 μrn (L × W) devices. The memory window obtained is about 1.3V with 200nm PGO and 13nm ZrO₂. It is also found that memory window is less dependent on device sizes.