宽带低噪声放大器ADS仿真与设计

介绍一种X波段宽带低噪声放大器（LNA）的设计。该放大器选用NEC公司的低噪声放大管NE3210S01（HJFET）,采用微带阻抗变换型匹配结构和两级级联的方式,利用ADS软件进行设计、优化和仿真。最后设计的放大器在10~13 GHz范围内增益为25.4 dB±0.3 dB,噪声系数小于1.8 dB,输入驻波比小于2,输出驻波比小于1.6。该放大器达到了预定的技术指标,性能良好。     

一种Ku波段低噪声放大器的设计

基于ADS和HFSS电磁仿真软件,设计了一种Ku波段低噪声放大器。放大器包含波导-微带转换单元和低噪声放大器两部分。波导-微带转换单元采用体积小,性能优良的微带探针型过渡,为提高转换性能和带宽,采用二阶λ/4阻抗变换结构来实现50Ω微带线与微带探针之间的阻抗匹配。低噪声放大器选用CDK公司生产的具有超低噪声和高增益的FET器件CKRF7512CK24晶体管,采用偏置电路、最小噪声匹配及最大输出增益匹配相结合的方案,实现了低噪声和高增益。实测结果表明,在11.5GHz～13.5GHz的频率范围内,该低噪声放大器的输入输出回波损耗均小于-10dB,噪声系数小于0.8dB。     

宽带低噪声放大器单片微波集成电路

从行波放大器设计理论出发,研制了一款基于低噪声GaAs赝配高电子迁移率晶体管(PHEMT)工艺设计的2~20 GHz单片微波集成电路(MMIC)宽带低噪声放大器。该款放大器由九级电路构成。为了进一步提高放大器的增益,采用了一个共源场效应管和一个共栅场效应管级联的拓扑结构,每级放大器采用自偏压技术实现单电源供电。测试结果表明,本款低噪声放大器在外加+5 V工作电压下,能够在2~20 GHz频率内实现小信号增益大于16 dB,增益平坦度小于±0.5 dB,输出P-1 dB大于14 dBm,噪声系数典型值为2.5 dB,输入和输出回波损耗均小于-15 dB,工作电流仅为63 mA,低噪声放大器芯片面积为3.1 mm×1.3 mm。     

程控增益低噪声宽带直流放大器的设计

介绍了程控增益低噪声宽带直流放大器的设计原理及流程。采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了程控增益低噪声宽带直流放大器,实现了输入电压有效值小于10mV,输出信号有效值最大可达10V,通频带为0～8MHz,增益可在0～50dB之间5dB的步进进行控制,最高增益达到53dB,且宽带内增益起伏远小于1dB的两级宽带直流低噪声放大器的设计。     

用于5.8G网络的高增益低噪声放大器设计

设计了一款适用于5.8G网络的高增益低噪声放大器,采用两级低噪声放大器级联的形式提高放大器的增益参数,进行了放大器输入端、输出端和级间阻抗匹配。采用ATF-551M4作为核心器件,使用ADS软件实现放大器直流偏置电路设计、稳定性设计及阻抗匹配电路设计,并且进行了两级低噪声放大器的联合仿真以及PCB版图设计。测试结果表明在5.725～5.825 GHz的工作频率范围内,低噪声放大器的噪声系数小于1.1 dB,增益大于20 dB,输入输出回波损耗小于-10 dB。     

一种采用新型复合沟道GaN HEMTs低噪声分布式放大器

设计研制了一种新型的低噪声分布式放大器,采用了栅长为1μm的低噪声复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT (CC-HEMT). 给出了低噪声分布式放大器的仿真和测试结果. 测试结果显示低噪声分布式放大器在2~10GHz频率范围内,输入和输出端口驻波比均小于2.0,相关增益大于7.0dB,带内增益波纹小于1dB . 在2~6GHz频率范围内,噪声系数小于5dB;在2~10GHz频率范围内,噪声系数小于6.5dB; 测试结果与仿真结果较吻合.     

采用幅度均衡器的宽带毫米波低噪声放大器

对微带型幅度均衡器进行了理论分析和计算机仿真。微带型均衡器由微带谐振器上加载电阻构成,电阻的引入有效地展宽了频带。通过优化支节的长度、宽带和电阻的阻值,得到满足要求的均衡器。利用这种均衡器,对采用两级毫米波宽带MMIC的放大器进行了增益修正,使增益平坦度得到有效改善,同时对噪声的影响也较小。采用幅度均衡器最终实现的低噪声放大器在频率范围26.5～40 GHz内,增益为26.5～28.5 dB,增益平坦度优于±1.5 dB,噪声小于3.3dB,输入输出端口驻波小于2.0,输出1 dB压缩点功率大于10 dBm。     

2～4GHz MMIC低噪声放大器

采用中国电子科技集团公司第十三研究所的GaAs PHEMT低噪声工艺,设计了一款2~4 GHz微波单片集成电路低噪声放大器(MMIC LNA)。该低噪声放大器采用两级级联的电路结构,第一级折中考虑了低噪声放大器的最佳噪声和最大增益,采用源极串联负反馈和输入匹配电路,实现噪声匹配和输入匹配。第二级采用串联、并联负反馈,提高电路的增益平坦度和稳定性。每一级采用自偏电路设计,实现单电源供电。MMIC芯片测试结果为:工作频率为2~4 GHz,噪声系数小于1.0 dB,增益大于27.5 dB,1 dB压缩点输出功率大于18 dBm,输入、输出回波损耗小于-10 dB,芯片面积为2.2 mm×1.2 mm。     

X波段高性能低噪声放大器的设计与实现

设计并实现了一种适用于X波段(11~12 GHz)的高性能低噪声放大器(LNA),该低噪声放大器选用Ga As FET(MGF4941AL)低噪声半导体管,采用三级级联的方式设计,三级通过采用不同静态工作点之间的配合,达到降低放大器噪声提高增益的目的。利用微波电路仿真软件ADS仿真优化后加工实物并测试。测试结果表明,低噪声放大器在11~12 GHz工作频带内的噪声系数小于2dB,输入/输出驻波比(VSWR)小于2,功率增益大于30 d B,增益平坦度小于1.5 d B,适用于X波段接收机前端。     

X波段低噪声放大器设计

针对目前X波段低噪声放大器的电路拓扑结构不易选择,故提出了一种采用微带分支线匹配结构和三级级联方式的X波段低噪声放大器(LNA)。放大器选用NEC低噪声放大管NE3210S01,利用ADS(Advanced Design System)软件设计、仿真、优化,放大器实测结果表明:在9.2 GHz～9.6 GHz频带内,噪声系数小于1.7 dB,带内增益达到33.5 dB,带内增益平坦度ΔG≤±0.3 dB,输入、输出驻波比均小于1.5。该放大器已应用于X波段接收机,效果良好,其设计方法可供工程应用参考。     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

1MHz～40GHz超宽带分布式低噪声放大器设计

为满足宽带系统中低噪声放大器(LNA)宽带的要求,采用0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,设计了两款1 MHz^40 GHz的超宽带LNA,分别采用均匀分布式放大器结构及渐变分布式放大器结构,电路面积分别为1.8 mm×0.85 mm和1.8 mm×0.8 mm。电磁场仿真结果表明,1 MHz^40 GHz频率范围内,均匀分布式LNA增益为15.3 dB,增益平坦度为2 dB,噪声系数小于5.1 dB;渐变分布式LNA增益为14.16 dB,增益平坦度为1.74 dB,噪声系数小于3.9 dB。渐变分布式LNA较均匀分布式LNA,显著地改善了增益平坦度、噪声性能和群延时特性。     

A wideband low noise amplifiers design incorporating the CMRC circuitry

An impedance bandwidth enhancement technique for tuning a low noise amplifier (LNA) is presented. With the use of the compact microstrip resonant cell (CMRC) at the emitter pins of a bipolar junction transistor (BJT), the impedance bandwidth achieved is about 95%, for a simple single stage amplifier design. The LNA attains a gain of about 15 dB; also a low noise figure of 1.16 dB at 2.1GHz and an average noise figure of about 1.5 dB across the operation bands have been achieved.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz60 MHz low noise amplifier (LNA) designed in a 0.35 m SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point (IP1dB) of ?11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

Millimeter‐Wave High‐Linear CMOS Low‐Noise Amplifier Using Multiple‐Gate Transistors

A millimeter‐wave (mm‐wave) high‐linear low‐noise amplifier (LNA) is presented using a 0.18 µm standard CMOS process. To improve the linearity of mm‐wave LNAs, we adopted the multiple‐gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate‐source bias at the last stage of LNAs, third‐order input intercept point (IIP3) and 1‐dB gain compression point (P_1dB) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

High-performance in W-band monolithic pseudomorphic InGaAsHEMT LNA's and design/analysis methodology

High-performance W-band monolithic one- and two-stage low noise amplifiers (LNAs) based on pseudomorphic InGaAs-GaAs HEMT devices have been developed. The one-stage amplifier has a measured noise figure of 5.1 dB with an associated gain of 7 dB from 92 to 95 GHz, and the two-stage amplifier has a measured small signal gain of 13.3 dB at 94 GHz and 17 dB at 89 GHz with a noise figure of 5.5 dB from 91 to 95 GHz. An eight-stage LNA built by cascading four of these monolithic two-stage LNA chips demonstrates 49 dB gain and 6.5 dB noise figure at 94 GHz. A rigorous analysis procedure was incorporated in the design, including accurate active device modeling and full-wave EM analysis of passive structures. The first pass success of these LNA chip designs indicates the importance of a rigorous design/analysis methodology in millimeter-wave monolithic IC development     

0.2μm GaAs PHEMT3.1~10.6GHz宽带低噪声放大器设计

采用OMMIC公司提供的0.2μm GaAs PHEMT工艺(fT=60 GHz)设计并实现了一种适用于宽带无线通信系统接收前端的低噪声放大器。在3.1~10.6 GHz的频带内测试结果如下:最高增益为13 dB;增益波动<2dB;输入回波损耗S11<-11 dB;输出回波损耗S22<-16 dB;噪声系数NF<3.9 dB。5 V电源供电,功耗为120mW。芯片面积为0.5 mm×0.9 mm。与近期公开发表的宽带低噪声放大器测试结果相比较,本电路结构具有芯片面积小、工作带宽大、噪声系数低的优点。