A visualization-based approach for bump-pad/IO-ball placement and routing in flip-chip/BGA technology

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computer-aided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.     

Finite element modeling of electronic packages subjected to drop impact

As more electronic products become portable, many product manufacturers have started to pay more attention to the robustness of their products. Finite element (FE) simulation has become increasingly popular in the analysis of products subjected to impact loading. The need for details in a FE mesh is always balanced by considerations of simulation time and available computational resources. In this paper, three commonly used approaches to FE modeling of a ball grid array (BGA) package subjected to drop impact are evaluated. The first model comprises a detailed mesh of the printed circuit board (PCB), integrated circuit (IC) package and interconnecting solder balls using solid three-dimensional (3-D) elements. The degrees of freedom is reduced for the second mesh by using shell elements for the PCB and IC package while retaining the detailed mesh of the solder balls using solid 3-D elements. The third mesh is a further simplification of the second mesh whereby the solder balls are replaced by a single beam element each. The stresses within the solder balls are then obtained in a separate FE analysis of a detailed solder ball mesh using the displacement history of nodes around the beam elements from the previous analysis as inputs. Solder ball stresses from all three meshes were found to differ by as much as 40% although PCB deflection compared favorably.     

Implementing ASIC/memory integration by system-on-package

A system-on-package (SOP) solution of an application specific integrated circuit (ASIC) chip integrating with an embedded data output (EDO) memory die has been realized. Both chips are assembled into a new form factor that appears as a standard plastic ball grid array (PBGA) with 90 balls and 1.27 mm ball pitch. Topically, size reduction of approximately 60% over the equivalent printed circuit board implementation is achieved. Other benefits include simplified board design and reduction in material cost. Assembly processes are expressed to indicate how this package is made. Reliability analyzes such as: pre-conditioning, temperature cycle test (TCT), and pressure cook test (PCT), are conducted     

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

Application of the Taguchi method to chip scale package (CSP)design

A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS^TM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L₁₈ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls     

Material property effects on solder failure analyses

The effects of material properties modeling on the solder failure analyses by numerical simulations are studied. The packaging structure of plastic ball grid array on printed circuit board was modeled. Two different types of molding compounds and two different types of substrates were employed and combined for the plastic ball grid array package modeling. The material properties were assumed as temperature dependent elastic and viscoelastic, and finite element method was used to calculate and analyze the strain energy densities of the solder balls. The chip warpage was also studied, and related with the solder ball reliability analyses by discussing the viscoelastic characteristics of the materials and their influences on the deformations. The results showed that the warpage developments of the packaging structure showed very different behaviors, and the mechanism of the strain energy density accumulations in the solder balls were also different depending on the material properties modeling and their combinations. This study demonstrates that appropriate modeling of the material properties is critical for the interpretation and understanding the microelectronics reliability mechanisms.     

Broadband BGA-Via Transitions for Reliable RF/Microwave LTCC-SiP Module Packaging

This letter presents two broadband ball grid array-via transition structures applicable in reliable radio frequency/microwave low-temperature co-fired ceramic system-in-package (LTCC-SiP) module packaging from dc up to the K-band. The first transition provides better electromagnetic shielding, while the second one exhibits 40% wider bandwidth by including an air-cavity in the LTCC module. To specifically address board-level reliability, novel plastic-core solder balls as large as 1100 mum were employed. The measured 1-dB cutoff frequencies of the transition structures, all the way from the printed circuit board up to the top surface of the module package, were 19 and 27 GHz. In addition, equivalent circuit models for the transitions were developed.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

BGA器件Z×2101回流过程有限元模拟

采用间接耦合的方法对BGA（Ball Grid Array）器件ZX2101的回流过程进行有限元模拟,得出回流结束后BGA器件整体、PCB以及芯片基板的温度分布,同时仿真分析了焊球阵列部分的温度分布随时间变化的情况,据此得到回流结束后PCB与芯片基板的变形。在设定的温度边界条件下,得到了四点回流曲线,模拟结果与实测结果相吻合。     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case     

A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables     

Integrated circuit ceramic ball grid array package antenna

The recent advances in such highly integrated RF transceivers as radio system-on-chip and radio system-in-package have called for the parallel development of compact and efficient antennas. This paper addresses the development of a new type of dielectric chip antenna known as integrated circuit package antenna (ICPA) for highly integrated RF transceivers. A compact ICPA of this type has, for the first time, been designed and fabricated in a ceramic ball grid array (CBGA) package format. The novel ICPA, except economical advantage of mass production and automatic assembly, has potential benefit to the system-level board miniaturization and the system-level manufacturing facilitation. The simulated and measured antenna performance of the ICPA is presented. The effects of the different physical parts of the ICPA on the antenna performance are investigated. Results show that the ICPA achieved impedance bandwidth of 4.1% and radiation efficiency of 72%, and gain of 4.8 dBi at 5.715 GHz.     

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

Development of CSP using Au ball bumps as external connection terminals

We developed a new-structure, fine-pitch chip size package (CSP) with Au ball bumps used as external connection terminals. In the manufacturing process, a substrate consisting of a base material made of a Cu alloy (0.3Cr-0.25Sn-0.2Zn-Cu) and spot Ag plating applied to one side was used as a temporary interposer. After the molding process, only the substrate was dissolved selectively, and an interposer-less structure was realized. We founded that we can directly connect Au ball bumps to tip balls of Au wires exposed on the back surface of a package by applying etching dissolution to a substrate. Thus, terminals can now be arranged in as fine a pitch as a wire bonding pitch. We verified that each bond between a Au ball bump and a Au wire has sufficient strength, and the strength did not decrease after 1000 cycles of -55/spl deg/C/+125/spl deg/C. We attempted mounting on board using the Au-Au bonding method with an insulating adhesive. No void occurred in the connection areas, and the electrodes on the substrate were properly deformed and connected. After 1400 cycles of -55/spl deg/C/+125/spl deg/C, electric resistance of interconnect portion did not decrease, and thus, a high degree of mounting reliability was confirmed.     

Enhanced solder joint bonding strength of electronic packaging with electrowetting effect

This paper reports a novel method to enhance solder ball or solder ring bonding strength by using electrowetting-on-dielectric (EWOD) effect. With a low melting point, the metal Sn has been widely used in electronic packaging technology. Since Sn will be molten into liquid when the temperature is increased above the melting point, the method for treating liquid can be herein employed. Contact angle of the molten Pb-free balls or ring structure on silicon substrate have been experimentally changed by applying electric field across the thin dielectric film between the molten solder and the conductive silicon substrate. The contact area between the solder and the substrate is enlarged due to the decrease of the contact angle. Our testing results on the EWOD enhanced packaging structures of solder balls, flip-chip and solder ring hermetic package generally show about 50% enhancement in bonding shear strength. The significantly enhanced solder link bonding strength is hopeful for improving packaging reliability and is promising to be used in high performance silicon based electronic or microelectromechanic SiP (system in package) technologies.     

Experimental and numerical investigation of flow and thermal effects on flexible printed circuit board

The desire of flexibility, compact, lightweight and low cost in current electronic device increases the application of flexible printed circuit board (FPCB). However, FPCB would encounter significant deflection and stress under operating condition (thermal factor) with air flow cooling system as compared to rigid printed circuit board (RPCB). Therefore, present study aims to investigate the effects of airflow rate and heat on FPCB attached with a ball grid array (BGA) package using experimental and numerical method. In this present study, the simulation was carried out by using FLUENT and ABAQUS, coupled in real time by Mesh-based Parallel Code Coupling Interface (MpCCI) where flow and thermal effects were coupled simultaneously. The experiments were conducted in a wind tunnel with the BGA package on the FPCB. Low discrepancy between simulation and experimental results indicated that the proposed numerical simulation method is proven to be reliable and sufficient to study the FPCB with thermal and flow effects which has not been established by previous researchers. The findings also showed that the Reynolds number and heat have significant effects on FPCB's deflection and stress. Therefore, it is important to include thermal effect when dealing with FPCB under flow environment. The outcomes of this paper can be a guideline to the FPCB industries.     

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

Processing of fluxing underfills for flip chip-on-laminate assembly

Fluxing underfill eliminates process steps in the assembly of flip chip-on-laminate (FCOL) when compared to conventional capillary flow underfill processing. In the fluxing underfill process, the underfill is dispensed onto the board prior to die placement. During placement, the underfill flows in a "squeeze flow" process until the solder balls contact the pads on the board. The material properties, the dispense pattern and resulting shape, solder mask design pattern, placement force, placement speed, and hold time all impact the placement process and the potential for void formation. A design of experiments was used to optimize the placement process to minimize placement-induced voids. The major factor identified was board design, followed by placement acceleration. During the reflow cycle, the fluxing underfill provides the fluxing action required for good wetting and then cures by the end of the reflow cycle. With small, homogeneous circuit boards it is relatively easy to develop a reflow profile to achieve good solder wetting. However, with complex SMT assemblies involving components with significant thermal mass this is more challenging.