A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.     

A VLSI-Suitable Schottky-Barrier CMOS Process

Trenched Schottky-barrier (TSB) contact PMOS devices for use in latchup-free CMOS are examined in detail, and compared to Schottky-contact PMOS. Measurements and simulations show that the TSB structure has significant advantages in gain and current leakage over the Schottky-contact structure, CMOS using TSB PMOS may be made unconditionally free of Iatchup. The tradeoffs involving PMOS source-drain implant dose are made explicit and correlated to Iatchup measurements.     

Submillimeter-Wave Detection with Submicron-Size Schottky-Barrier Diodes

Schottky-barrier diode detection has been extended to 7.2 THz (42 mu m) using 0.5-mu m-diam diodes. The diodes were fabricated on bulk-doped n-type GaAs using electron lithographic techniques; diameters as small as 1000 /spl Aring/ have been achieved. A new approach in Schottky-barrier design, the contact array diode, is proposed. The diode is fabricated from readily available bulk doped material, and a performance is indicated that is competitive to the conventional epitaxial Schottky-barrier mixer well into the submillimeter wavelength region. A scanning electron microscope (SEM) photograph of diode array structures is shown.     

A Nonlinear Analysis of Schottky-Barrier Diode Upconverters

A nonlinear computer analysis of Schottky-barrier diode upconverters by means of obtaining the steady-state solutions of differential equations characterized by the diode and connected circuits is shown. Both the nonlinearities of barrier resistance and capacitance are taken into consideration. The waveforms of the voltage and current at the diode, impedance, and input-output power relationships are computed for 120-GHz upconverters.     

A static random-access memory with normally-off-type Schottky barrier FET's

A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.     

A new model for modulation-doped FET's

A new study showing that Lehovec and Zuleeg analysis for silicon FET's can be extended to the GaAs FET's is presented. An analytical model that effectively predicts the characteristics of the MODFET is introduced. The agreement between the model and the experimental data appears to be very good.     

Submillimeter Heterodyne Detection with Planar GaAs Schottky-Barrier Diodes

Planar surface-oriented Pt/GaAs Schottky-barrier diodes have been fabricated and used to detect signals at submillimeter wavelengths. Video detection has been observed up to frequencies as high as 890 GHz. Harmonic mixing between the ninth harmonic of a 74.21-GHz signal and the second harmonic of 333.95-GHz radiation has also been obtained.     

GaAs ultra-high-frequency dividers with advanced SAINT FET's

The circuit design, fabrication, and performance of ultra-high-frequency dividers with buffer FET logic (BFL) circuits are described. Using air-bridge technology and a new, self-aligned-gate, GaAs FET process, called advanced SAINT, which avoids excess gate metal overlap on the dielectric film, 10.6-GHz operation at 258 mW is achieved. This performance is made possible by a reduction of gate and interconnection parasitic capacitance. Furthermore, the possibility of operation above 20 GHz for GaAs MESFET frequency dividers is predicted on the basis of circuit optimization and FET improvements including parasitic capacitance reduction and transconductance enhancement.     

Microwave Amplifier Design with Potentially Unstable FET's

The concept of maximally efficient gain, as applied to the design of microwave transistor amplifiers with potentially unstable devices, is illustrated by an example, utilizing the parameters of a typical small-signal microwave FET.     

A Spice Model for Enhancement-and Depletion-Mode GaAs FET's

An improved model for the GaAs MESFET has been implemented in the source code of the circuit-simulation program SPICE. New features include 1) an accurate model for the Schottky barrier, which allows simulation of both enhancement- and depletion-mode devices; 2) detailed modeling of the nonlinear gate-source and gate-drain capacitance; and 3) a user-specifiable value for the exponent in the expression for the dependence of the dc drain current upon the gate-source voltage. Also discussed are some important points concerning the charge-voltage equations that must accompany the new model's capacitance-voltage equations within SPICE. The new GaAs FET SPICE model is believed to be the most comprehensive one available to date in the public domain.     

High-frequency noise measurements on FET's with small dimensions

A low-noise high-frequency transresistance amplifier has been used to accurately measure broad-band noise in MOSFET's with small widths and submicrometer channel lengths. The technique allows noise characterization up to frequencies of 100 MHz of the small devices available as process test arrays from different fabrication lines. The noise in the different portions of theI-Vcharacteristics of submicrometer MOSFET's has been characterized and shown to be greater by factors of 2 to 4 than the noise expected from long-channel noise theory.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

Noise in GaAs FET's with a nonuniform channel thickness

The effects of nonuniformities in the channel thickness of a GaAs FET are investigated and expressions for the dc, small signal, and noise parameters derived. Results of a numerical simulation show that higher transconductance and lower noise would result if the variations in channel thickness were reduced. Experimental evidence shows that the predictions of this model are significant at the 5-percent level.     

GaAs FET's with a flicker-noise corner below 1 MHz

GaAs MESFET's with significantly reduced low-frequency noise are demonstrated through application of an understanding that the dominant noise source is generation-recombination (g-r) noise from deep level traps in the gate and backside depletion layers. A 1/f noise spectrum measured from 100 Hz to 10 MHz is modeled as the sum of Lorentzian noise spectra from a few traps subject to the temperature distribution inherent in a GaAs MESFET. The noise associated with a single mid-bandgap trapping level does not appear as an ideal Lorentzian, but rather as 1/f over nearly a decade frequency range by virtue of a time constant that is a strong function of temperature ( exp[Ea/ kT]) and an estimated temperature distribution of 22°C across the active region. The major g-r trap was characterized as having an activation energy of 0.75 eV. By reducing the g-r noise, flicker noise was decreased by more than 15 dB compared to our conventional GaAs MESFET's and the noise corner was reduced to less than 1 MHz from a typical 40 MHz. This significant reduction was achieved by using MBE layers designed to have lower trap concentrations and high channel doping. These results are within 10 dB of the estimated 1/f noise limit due to the quantum mechanics of carrier scattering [5], [14].     

High-power conductivity-modulated FET's (COMFET's) with a p-type channel

In previous work, a conductivity-modulated field-effect transistor (COMFET) having drastically reduced on-resistance was described; that device was based on n-channel MOS technology. In this letter, we report the development of a complementary device-the p-channel COMFET. These new p-channel COMFET's have demonstrated dc on-resistance values as low as 0.07 Ω at 20 A (for a 3 mm × 3 mm pellet), while providing forward blocking voltages of 200-400 V. To our knowledge, this on-resistance value (normalized to the same active area) is lower than that of any p-channel power MOSFET (even those with blocking voltages of only 100 V) and as much as 30 times less than that of a p-channel MOSFET with a comparable blocking-voltage capability. Using suitable minority-carrier-lifetime control techniques, drain-current-decay times have been reduced from ≈ 30 µs to below 1 µs.     

InAlAs/InGaAs heterostructure FET's processed with selectivereactive-ion-etching gate-recess technology

A highly selective reactive-ion-etching process based on HBr plasma has been used as a gate-recess technique in fabrication of InAlAs/InGaAs heterostructure FETs. A typical 0.75-μm-gate-length transistor exhibited a threshold voltage of -1.0 V, a maximum extrinsic transconductance of 600 mS/mm, an extrinsic current-gain cutoff frequency of 37 GHz, and a maximum frequency of oscillation of 90 GHz. These DC and RF device parameters compare favorably with those of a corresponding device gate-recessed with a selective wet-etching technique     

Submicron GaAs microwave FET's with low parasitic gate and source resistances

The substantial reduction in gate metallization resistance and improvement in performance of submicron-gate GaAs FET's has been achieved by employing a mushroom profile defined by electron-beam exposure. Using MBE growth of buffer, channel, and n+ contact layers, minimum noise figures of 1.0-1.1 dB have been demonstrated at 8 GHz, with associated gains of 13-14 dB.     

A new extraction method to determine bias-dependent source seriesresistance in GaAs FET's

A new method is proposed to determine bias-dependent source resistances for GaAs field-effect transistors (FET's). This method, which is a cold-FET measurement technique, utilizes the relations between the real part of the two-port impedances transformed from the measured S-parameters and their algebraic derivatives. It is based on the fact that the algebraic derivatives of the two-port resistances result in the simple form at the normal cold-FET condition. A bias-independent gate resistance is extracted at the pinched-off cold-FET condition to fulfill necessary and sufficient conditions in extraction. The proposed method is a direct measurement because only algebraic calculation is required, and it is general enough to need only one assumption of the laterally symmetric channel-doping profile. The deleterious results of dispersion (frequency dependence) and negative value in source resistances at the pinched-off cold-FET condition are explained by the effects of the leakage current and the on-wafer pad parasitics, respectively. The problem of deviation of α₂₁ and α₁₂ from 0.5 at the normal cold-FET condition is also resolved by deembedding the on-wafer pad parasitics. This method allows one to extract bias-dependent source resistances for GaAs FET's     

Passivation of GaAs FET's with PECVD silicon nitride films ofdifferent stress states

The passivation of GaAs MESFETs with plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride films of both compressive and tensile stress is reported. Elastic stresses included in GaAs following nitride passivation can produce piezoelectric charge density, which results in a shift of MESFET characteristics. The shift of MESFET parameters due to passivation was found to be dependent on gate orientation. The experiments show that nitride of tensile stress is preferable for MESFETS with [011-bar] oriented gates. The shifts in V_TH,I_DSS, and G_M of the devices before and after nitride passivation are less than 5% if the nitride of appropriate stress states are used for passivation. The breakdown voltage of the MESFETs after nitride deposition was also studied. It is found that the process with higher hydrogen incorporation tends to reduce the surface oxide and increase the breakdown voltage after nitride deposition. In addition, the passivation of double-channel HEMTs is reported for the first time     

A quantitative comparison between calculated and measured conversion losses of a novel beam-lead GaAs Schottky-Barrier mixer diode with minimized parasitics

The conversion loss of a mixer diode is calculated as functions of the diode characteristics including the idealn-factor. Good agreement between the calculated and measured results is demonstrated by using both a novel beam-lead GaAs mixer diode with minimized parasitics and an improved test fixture for measuring the loss of this device.