Solution-processed ambipolar organic field-effect transistors and inverters

There is ample evidence that organic field-effect transistors have reached a stage where they can be industrialized, analogous to standard metal oxide semiconductor (MOS) transistors. Monocrystalline silicon technology is largely based on complementary MOS (CMOS) structures that use both n-type and p-type transistor channels. This complementary technology has enabled the construction of digital circuits, which operate with a high robustness, low power dissipation and a good noise margin. For the design of efficient organic integrated circuits, there is an urgent need for complementary technology, where both n-type and p-type transistor operation is realized in a single layer, while maintaining the attractiveness of easy solution processing. We demonstrate, by using solution-processed field-effect transistors, that hole transport and electron transport are both generic properties of organic semiconductors. This ambipolar transport is observed in polymers based on interpenetrating networks as well as in narrow bandgap organic semiconductors. We combine the organic ambipolar transistors into functional CMOS-like inverters.     

Single electron transistor with P-type sidewall spacer gates

A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed.     

An electron microscopy investigation of the structure of porous silicon by oxide replication

The morphology of porous silicon is studied by scanning electron microscopy (SEM) by making an oxide replica of the pore structure. Highly branched n-type porous silicon samples were prepared and a replica was formed by oxidation of the pores followed by selective removal of the silicon substrate to expose the oxide pores. Scanning and transmission electron microscopy images confirmed many previously held assumptions about porous silicon formation, including the fractal structure and crystallographic propagation; they also provided a clearer understanding of the details of pore formation. The replica procedure also provides a platform for a more facile and comprehensive analysis of the porous silicon morphology.     

Selective etching of n-type silicon in pn junction structure in hydrofluoric acid and its application in silicon nanowire fabrication

Boron is selectively implanted on the surface of an n-type silicon wafer to form a p-type area surrounded by an n-type area. The wafer is then put into a buffered oxide etch solution. It is found that the n-type area can be selectively etched without illumination, with an etching rate lower than 1?nm?min(-1), while the p-type area can be selectively etched under illumination with a much higher etching rate. The possible mechanism of the etching phenomenon is discussed. A simple fabrication process of silicon nanowires is proposed according to the above phenomenon. In this process only traditional micro-electromechanical system technology is used. Dimensions of the fabricated nanowire can be controlled well. A 50?nm wide and 50?nm thick silicon nanowire has been formed using this method.     

Patterning and Templating for Nanoelectronics

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top‐down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top‐down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next‐generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.     

Wet route to silicon oxide quantum dots with fixed and strong blue emission

Amorphous silicon oxide quantum dots, with a quantum yield of 0.47 and blue emission fixed at 2.85 eV (433 nm), were obtained via two wet steps: first silicon nanowires reacted with potassium hydroxide at 50 °C, and then the resultants were kept in the dark and exposed to air at 20 °C. The silicon nanowires were synthesized in a high-temperature tube furnace using quartz powder and hydrogen as starting materials, and these products had less oxide outer cover and were ready to react with potassium hydroxide. The transmission electron microscopy was employed in order to characterize the amorphous quantum dots of silicon oxide.     

Three-dimensional simulation of realistic single electron transistors

We present an approach, and its implementation in a computer program, for the three-dimensional (3-D) simulation of realistic single electron transistor (SET) structures, in which subregions with different degrees of quantum confinement are simultaneously considered. The proposed approach is based on the self-consistent solution of the many body Schrodinger equation with density functional theory and on the computation of the conductance of tunnel constrictions through the solution of the 3-D Schrodinger equation with open boundary conditions. We have developed an efficient code (ViDES) based on such an approach. As examples of addressable SET structures, we present the simulation of a SET, one defined by metal gates on an AlGaAs/GaAs heterostructures, and of a SET defined by etching and oxidation on the silicon-on-insulator material system. Since SETs represent prototypical nanoscale devices, the code may be a valuable tool for the investigation and optimization of a broad range of nanoelectronic solid-state devices.     

Influence of electron irradiation on the electronic transport mechanisms during the conductive AFM imaging of InAs/GaAs quantum dots capped with a thin GaAs layer

We have used conductive atomic force microscopy (C-AFM) to study the electronic transport mechanisms through InAs quantum dots (QDs) grown by molecular beam epitaxy on an n-type GaAs(001) substrate and covered with a 5?nm thick GaAs cap layer. The study is performed with a conductive atomic force microscope working inside a scanning electron microscope. Electric images can be obtained only if the sample is preliminarily irradiated with an electron probe current sufficiently high to generate strong electron beam induced current. In these conditions holes are trapped in QDs and surface states, so allowing the release of the Fermi level pinning and thus conduction through the sample. The electronic transport mechanism depends on the type of AFM probe used; it is explained for a metal (Co/Cr) coated probe and p-doped diamond coated probe with the aid of energy band diagrams. The writing (charge trapping) and erasing (untrapping) phenomena is conditioned by the magnitude of the electron probe current. A strong memory effect is evidenced for the sample studied.     

Ordered arrays of <100>-oriented silicon nanorods by CMOS-compatible block copolymer lithography

Dense, ordered arrays of <100>-oriented Si nanorods with uniform aspect ratios up to 5:1 and a uniform diameter of 15 nm were fabricated by block copolymer lithography based on the inverse of the traditional cylindrical hole strategy and reactive ion etching. The reported approach combines control over diameter, orientation, and position of the nanorods and compatibility with complementary metal oxide semiconductor (CMOS) technology because no nonvolatile metals generating deep levels in silicon, such as gold or iron, are involved. The Si nanorod arrays exhibit the same degree of order as the block copolymer templates.     

Tunable visible and near-IR emission from sub-10 nm etched single-crystal Si nanopillars

Visible and near-IR photoluminescence (PL) is reported from sub-10 nm silicon nanopillars. Pillars were plasma etched from single crystal Si wafers and thinned by utilizing strain-induced, self-terminating oxidation of cylindrical structures. PL, lifetime, and transmission electron microscopy were performed to measure the dimensions and emission characteristics of the pillars. The peak PL energy was found to blue shift with narrowing pillar diameter in accordance with a quantum confinement effect. The blue shift was quantified using a tight binding method simulation that incorporated the strain induced by the thermal oxidation process. These pillars show promise as possible complementary metal oxide semiconductor compatible silicon devices in the form of light-emitting diode or laser structures.     

Extended arrays of vertically aligned sub-10 nm diameter [100] Si nanowires by metal-assisted chemical etching

Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal film affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal film. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 10 (10) wires/cm (2) were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.     

Rapid and Low‐Cost Prototyping of 3D Nanostructures with Multi‐Layer Hydrogen Silsesquioxane Scaffolds

A layer‐by‐layer (LBL) method can generate or approximate any three‐dimensional (3D) structure, and has been the approach for the manufacturing of complementary metal‐oxide‐semiconductor (CMOS) devices. However, its high cost precludes the fabrication of anything other than CMOS‐compatible devices, and general 3D nanostructures have been difficult to prototype in academia and small businesses, due to the lack of expensive facility and state‐of‐the‐art tools. It is proposed and demonstrated that a novel process that can rapidly fabricate high‐resolution three‐dimensional (3D) nanostructures at low cost, without requiring specialized equipment. An individual layer is realized through electron‐beam lithography patterning of hydrogen silsesquioxane (HSQ) resist, followed by planarization via spinning SU‐8 resist and etch‐back. A 4‐layer silicon inverse woodpile photonic crystal with a period of 650 nm and a 7‐layer HSQ scaffold with a period of 300 nm are demonstrated. This process provides a versatile and accessible solution to the fabrication of highly complex 3D nanostructures.     

Electron transport in pure and doped hematite

Hematite (α-Fe(2)O(3)) is a promising candidate for photoelectrochemical splitting of water. However, its intrinsically poor conductivity is a major drawback. Doping hematite to make it either p-type or n-type enhances its measured conductivity. We use quantum mechanics to understand how titanium, zirconium, silicon, or germanium n-type doping affects the electron transport mechanism in hematite. Our results suggest that zirconium, silicon, or germanium doping is superior to titanium doping because the former dopants do not act as electron trapping sites due to the higher instability of Zr(III) compared to Ti(III) and the more covalent interactions between silicon (germanium) and oxygen. This suggests that use of n-type dopants that easily ionize completely or promote covalent bonds to oxygen can provide more charge carriers while not inhibiting transport.     

Submicron metal patterns of arbitrary geometry fabricated by means of selective removal of oxygen atoms from molybdenum oxide

The possibility of manufacturing metal patterns with submicron linear elements on a silicon substrate by means of the selective removal of oxygen atoms from metal oxide is demonstrated for the first time. Structures of 0.35-μm-wide molybdenum stripes with a thickness of 20 nm have been obtained using 3-keV proton irradiation of a molybdenum oxide film on a silicon substrate via an electron-beam resist mask, followed by removal of the resist and the non-reduced oxide regions. The proposed method can be used for the fabrication of submicron metal patterns of arbitrary geometry on various substrates.     

Reliability challenges for low voltage/low power integrated circuits

This review paper discusses reliability considerations for low voltage/low power integrated circuit technologies. This growing market will continue to be dominated by scaled CMOS, with silicon on insulator technology growing in importance due to improved performance and reliability over bulk, low power CMOS. Power dissipation, performance, and reliability will be traded off at all levels of system design; this paper concentrates on device level issues. An aggressive low voltage/low power technology development path could yield a CMOS/SOI technology with 40 nm junctions, 5 nm gate oxides, and 0·9 V supplies. Such an aggressive low voltage/low power technology alters many traditional reliability problems such as metallization failure, oxide breakdown, hot carrier effects, electrostatic discharge, leakage currents, soft errors and analogue circuit noise. SOI brings additional reliability concerns such as heat dissipation through the buried oxide, bipolar latch, and back interface effects. This paper examines several of these issues and identifies a number of present and future reliability challenges for low voltage/low power technology.     

Bandgap engineered graphene and hexagonal boron nitride for resonant tunnelling diode

In this article a double-barrier resonant tunnelling diode (DBRTD) has been modelled by taking advantage of single-layer hexagonal lattice of graphene and hexagonal boron nitride (h-BN). The DBRTD performance and operation are explored by means of a self-consistent solution inside the non-equilibrium Green’s function formalism on an effective mass-Hamiltonian. Both p- and n-type DBRTDs exhibit a negative differential resistance effect, which entails the resonant tunnelling through the hole and electron bound states in the graphene quantum well, respectively. The peak-to-valley ratio of approximately 8 (3) for p-type (n-type) DBRTD with quantum well of 5.1 nm (4.3 nm) at a barrier width of 1.3 nm was achieved for zero bandgap graphene at room temperature.     

Ballistic electron emission from quantum-sized nanosilicon diode and its applications

A quantum confinement effect renders silicon a functional wide-gap material with useful functions. For instance, a diode based on nanocrystalline silicon (nc-Si) exhibits characteristic quasi-ballistic emission effects in various media. As means for physical excitation and probing, the applicability to parallel electron beam lithography and high-sensitivity image-pickup has been demonstrated in vacuum. The energetic electron incidence into air and Xe ambient induces negative ion generation by electron attachment into oxygen molecules and vacuum ultraviolet light emission by internal excitation of Xe molecules, respectively. Another effect is that the nc-Si ballistic emitter can supply highly reducing electrons into aqueous and metal-salt solutions without the use of counter electrodes. This is an attractive process that will be applicable to hydrogen generation and thin metal film deposition.     

Emission properties of DLC films on Si substrates

DLC films were deposited on polished both n-type and p-type silicon substrates. The silicon resistivity was ～0.02 Θ cm. Some of the DLC films 20 nm thick were deposited on the n-type Si surface with the submicron cones. SEM and Raman spectroscopy were used for structural investigations. Field electron emission occurs after dielectric breakdown, except for the samples with Si cones for which the emission seems to originate from SiC formed during the first stage of electron emission. It seems that too much sp² graphite phase may give rise to the observed increase in the turn-on field from 50 V/μm up to 150 V/μm.     

Fabrication of solid-state nanopores with single-nanometre precision

Single nanometre-sized pores (nanopores) embedded in an insulating membrane are an exciting new class of nanosensors for rapid electrical detection and characterization of biomolecules. Notable examples include alpha-hemolysin protein nanopores in lipid membranes and solid-state nanopores in Si3N4. Here we report a new technique for fabricating silicon oxide nanopores with single-nanometre precision and direct visual feedback, using state-of-the-art silicon technology and transmission electron microscopy. First, a pore of 20 nm is opened in a silicon membrane by using electron-beam lithography and anisotropic etching. After thermal oxidation, the pore can be reduced to a single-nanometre when it is exposed to a high-energy electron beam. This fluidizes the silicon oxide leading to a shrinking of the small hole due to surface tension. When the electron beam is switched off, the material quenches and retains its shape. This technique dramatically increases the level of control in the fabrication of a wide range of nanodevices.     

Vapor-solid-solid growth of crystalline silicon nanowires using anodic aluminum oxide template

Silicon nanowires (SiNWs) were grown at low temperatures close to metal silicon eutectic point on a silicon substrate using gold catalyst coupled with assistance of the aluminum anodic oxide template. Either a vapor-solid-solid (VSS) growth process below metal silicon eutectic temperature or a vapor-liquid-solid (VLS) process at slightly higher temperatures was observed. The transmission electron microscopy coupled with both the X-ray energy dispersive spectroscopy and the selected area electron diffraction was adopted to characterize the SiNWs. Although the mechanism triggering the VSS process is still not clear, both the geometric and morphological characteristics of the SiNWs grown by the VSS process are discussed and compared with the SiNWs grown by the VLS process. The VSS SiNWs have a much slower growth rate (less than 100 nm/h), a smaller and more uniform diameter (in the range of 15.22 nm) due to a much slower rate of silicon diffusion and much smaller amount of silicon (6.8 wt.%) dissolved in the solid nanocatalyst.