Connection, a microcomputer program for storing and analyzing structural properties of neural circuits

The application of a microcomputer-based system (the Connection system) designed to deal with neuroanatomical information commonly analyzed by researchers and involved in the study of structural properties of neural circuits is presented. This system can be employed at first as a readily-accessible database containing physiological and anatomical data from nuclei of the central nervous system which define a network with up to 45 elements and their subdivisions and connections. Once the database from a specific network is built and stored in a file, routines of this system can be used to classify the nuclei in term of their afferents and efferents and also to display all possible pathways linking any pair of nuclei and their respective length (number of synapses). The role of such a system as an auxiliary tool in neuroanatomical and electrophysiological research is discussed by presenting the results obtained from the analysis of the neural circuits involved in cardiovascular function control in higher vertebrates.     

On the computational power of threshold circuits with sparse activity

Circuits composed of threshold gates (McCulloch-Pitts neurons, or perceptrons) are simplified models of neural circuits with the advantage that they are theoretically more tractable than their biological counterparts. However, when such threshold circuits are designed to perform a specific computational task, they usually differ in one important respect from computations in the brain: they require very high activity. On average every second threshold gate fires (sets a 1 as output) during a computation. By contrast, the activity of neurons in the brain is much sparser, with only about 1% of neurons firing. This mismatch between threshold and neuronal circuits is due to the particular complexity measures (circuit size and circuit depth) that have been minimized in previous threshold circuit constructions. In this letter, we investigate a new complexity measure for threshold circuits, energy complexity, whose minimization yields computations with sparse activity. We prove that all computations by threshold circuits of polynomial size with entropy O(log n) can be restructured so that their energy complexity is reduced to a level near the entropy of circuit states. This entropy of circuit states is a novel circuit complexity measure, which is of interest not only in the context of threshold circuits but for circuit complexity in general. As an example of how this measure can be applied, we show that any polynomial size threshold circuit with entropy O(log n) can be simulated by a polynomial size threshold circuit of depth 3. Our results demonstrate that the structure of circuits that result from a minimization of their energy complexity is quite different from the structure that results from a minimization of previously considered complexity measures, and potentially closer to the structure of neural circuits in the nervous system. In particular, different pathways are activated in these circuits for different classes of inputs. This letter shows that such circuits with sparse activity have a surprisingly large computational power.     

An efficient method of determining functional equivalence classes of a network with reconvergent fan-out

This paper is a study of the effects of the faults on tho functional operation of a combinational logic circuit. The conditions whereby two different faults can produce tho sancio functional output arc investigated. In this approach two fault graphs of the circuits arc drawn. By manipulating these fault graphs the faults which are functionally equivalent can be obtained. An algorithm for determining the functionally equivalent classes of faults in a combinational circuit is presented. The unique feature of the algorithm is that it produces tho true functional equivalence (not structural equivalence) even for the circuit with reconvergent fan-out with unequal parity.     

Evolutionary design of complex approximate combinational circuits

Functional approximation is one of the methods allowing designers to approximate circuits at the level of logic behavior. By introducing a suitable functional approximation, power consumption, area or delay of a circuit can be reduced if some errors are acceptable in a particular application. As the error quantification is usually based on an arithmetic error metric in existing approximation methods, these methods are primarily suitable for the approximation of arithmetic and signal processing circuits. This paper deals with the approximation of general logic (such as pattern matching circuits and complex encoders) in which no additional information is usually available to establish a suitable error metric and hence the error of approximation is expressed in terms of Hamming distance between the output values produced by a candidate approximate circuit and the accurate circuit. We propose a circuit approximation method based on Cartesian genetic programming in which gate-level circuits are internally represented using directed acyclic graphs. In order to eliminate the well-known scalability problems of evolutionary circuit design, the error of approximation is determined by binary decision diagrams. The method is analyzed in terms of computational time and quality of approximation. It is able to deliver detailed Pareto fronts showing various compromises between the area, delay and error. Results are presented for 16 circuits (with 27–50 inputs) that are too complex to be approximated by means of existing evolutionary circuit design methods.     

Volterra series analysis and synthesis of a neural network forvelocity estimation

The motion detection problem occurs frequently in many applications connected with computer vision. Researchers have studied motion detection based on naturally occurring biological circuits for over a century. In this paper, we propose and analyze a motion detection circuit which is based on nerve membrane conduction. It consists of two unidirectional neural networks connected in an opposing fashion. Volterra input-output (I-O) models are then derived for the network so that velocity estimation can be cast as a parameter estimation problem. The technique is demonstrated through simulation.     

减少自反馈测试硬件代价的两种方法

由被测电路自己施加测试向量的内建自测试方法把被测电路视为一种可利用的资源,而不仅仅是被测试的对象.通过将被测电路内部一些节点"反馈"连接到电路的输入端,被测电路可以在由外部加载初始测试向量之后,利用反馈顺序地产生并加载一组测试向量.对这种技术中的分组方法和反馈节点选取方法进行了改进,提出一种附加信息矩阵的面向多个特殊有向图的深度优先公共路径搜索方法和一种贪婪式反馈节点选取方法.对ISCAS85电路和MinTest测试集的仿真实验结果表明,这些方法可以有效减少硬件代价,并提高故障效率.     

Gibbs and Markov properties of graphs

Directed acyclic graphs (DAG's) and, more generally, chain graphs have in recent years been widely used for statistical modelling. Their Gibbs and Markov properties are now well understood and are exploited, e.g., in reducing the complexity encountered in estimating the joint distribution of many random variables. The scope of the models has been restricted to acyclic or recursive processes and this restriction was long considered imperative, due to the supposed fundamentally different nature of processes involving reciprocal interactions between variables. Recently however it was shown independently by Spirtes (Spirtes, 1995) and Koster (Koster, 1996) that graphs containing directed cycles may be given a proper Markov interpretation. This paper further generalizes the scope of graphical models. It studies a class of conditional independence (CI) probability models determined by a general graph which may have directed and undirected edges, and may contain directed cycles. This class of graphical models strictly includes the well-known class of graphical chain models studied by Frydenberg et al., and the class of probability models determined by a directed cyclic graph or a reciprocal graph, studied recently by Spirtes and Koster. It is shown that the Markov property determined by a graph is equivalent to the existence of a Gibbs-factorization of the density (assumed positive). To better understand the structural aspects of the Gibbs and Markov properties embodied by graphs the notion of lattice conditional independence (LCI), introduced by Andersson and Perlman (Andersson and Perlman, 1993), is needed. The Gibbs-factorization has an outer ‘skeleton’ which is determined by the ring of all anterior sets of the graph. This revised version was published online in June 2006 with corrections to the Cover Date.     

Recurrent neural network technique for behavioral modeling of power amplifier with memory effects

A new technique for behavioral modeling of power amplifier (PA) with short‐ and long‐term memory effects is presented here using recurrent neural networks (RNNs). RNN can be trained directly with only the input–output data without having to know the internal details of the circuit. The trained models can reflect the behavior of nonlinear circuits. In our proposed technique, we extract slow‐changing signals from the inputs and outputs of the PA and use these signals as extra inputs of RNN model to effectively represent long‐term memory effects. The methodology using the proposed RNN for modeling short‐term and long‐term memory effects is discussed. Examples of behavioral modeling of PAs with short‐ and long‐term memory using both the existing dynamic neural networks and the proposed RNNs techniques are shown. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:289–298, 2015.     

Demand-driven logic simulation using a network of loosely coupled processors

Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a ‘need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence.     

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y toπtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.     

Simplicity in Eulerian circuits: Uniqueness and safety

An Eulerian circuit in a directed graph is one of the most fundamental Graph Theory notions. Detecting if a graph G has a unique Eulerian circuit can be done in polynomial time via the BEST theorem by de Bruijn, van Aardenne-Ehrenfest, Smith and Tutte (1941–1951) [15], [16] (involving counting arborescences), or via a tailored characterization by Pevzner, 1989 (involving computing the intersection graph of simple cycles of G), both of which thus rely on overly complex notions for the simpler uniqueness problem.In this paper we give a new linear-time checkable characterization of directed graphs with a unique Eulerian circuit. This is based on a simple condition of when two edges must appear consecutively in all Eulerian circuits, in terms of cut nodes of the underlying undirected graph of G. As a by-product, we can also compute in linear-time all maximal safe walks appearing in all Eulerian circuits, for which Nagarajan and Pop proposed in 2009 [12] a polynomial-time algorithm based on Pevzner characterization.     

Using graph parsing for automatic graph drawing

This paper presents a procedure for automatically drawing directed graphs. Our system, Clan-based Graph Drawing Tool (CG), uses a unique clan-based graph decomposition to determine intrinsic substructures (clans) in the graph and to produce a parse tree. The tree is given attributes that specify the node layout. CG then uses tree properties with the addition of “routing nodes” to route the edges. The objective of the system is to provide, automatically, an aesthetically pleasing visual layout for arbitrary directed graphs. The prototype has shown the strengths of this approach. The innovative strategy of clan-based graph decomposition is the first digraph drawing technique to analyze locality in the graph in two dimensions. The typical approach to drawing digraphs uses a single dimension, level, to arrange the nodes     

Multi-level association rules and directed graphs for spatial data analysis

We propose a methodology that upgrades the methods of the Lagrangian analysis of surface sea-water parcels. This methodology includes data mining with efficient visualization techniques, namely, spatial–temporal association rules and multi-level directed graphs with different levels of space and time granularity. In the resulting multi-level directed graphs we can intertwine knowledge from various disciplines related to oceanography (in our application) and perform the mining of such graphs. We evaluate the proposed methodology on Lagrangian tracking of virtual particles in the velocity field of the numerical model called the Mediterranean Ocean Forecasting Model (MFS). We describe an efficient algorithm based on label propagation clustering, which finds cycles and paths in multi-level directed graphs and reveals how the number and size of the cycles depend on the seasons. In addition, we offer three interesting results of the visualization and mining of such graphs, that is, the 12 months periodicity of the exchange of water masses among sea areas, the separation of Mediterranean Sea circulation in summer and winter situations, obtained with the hierarchical clustering of multi-level directed graphs, and finally, with visualization with multi-level directed graphs we confirm the reversal of sea circulation in the Ionian Sea over the last decades. The aforementioned results received a very favorable evaluation from oceanographic experts.     

大脑中神经回路的电位发放比较

通过对大脑神经中存在的四个回路：嗅球网络、小脑皮层、海马结构和丘脑皮层,建立基于解剖的神经元回路模型,对四种神经元回路中神经元的动作电位进行数值模拟,通过外加刺激来研究四种回路的网络特性,得到丰富的发放模式,分析比较这四种回路中信息传递特性,模拟大脑中神经元网络信号传递特性.     

Representation of Edmonds' Algorithm for Finding Optimum Graph Branching on Associative Parallel Processors

In the paper, an efficient parallel implementation of Edmonds' algorithm is suggested for finding optimum graph branching on an abstract model of the SIMD type with vertical data processing (STAR machine). For this, associative parallel algorithms for finding critical circuit and its contraction, as well as for unfolding embedded critical circuits, are constructed for directed weighted graphs represented as a list of arcs and their weights. It is shown that the execution of Edmonds' algorithm on a STAR machine requires O(nlogn) time, where nis the number of graph vertexes. Basic advantages of the parallel implementation of Edmonds' algorithm compared to its implementation on sequential computers are discussed.     

Recursive processing of cyclic graphs

Recursive neural networks are a powerful tool for processing structured data. According to the recursive learning paradigm, the input information consists of directed positional acyclic graphs (DPAGs). In fact, recursive networks are fed following the partial order defined by the links of the graph. Unfortunately, the hypothesis of processing DPAGs is sometimes too restrictive, being the nature of some real-world problems intrinsically cyclic. In this paper, a methodology is proposed, which allows us to process any cyclic directed graph. Therefore, the computational power of recursive networks is definitely established, also clarifying the underlying limitations of the model.     

Development of tests for VLSI circuit testability at the upper design levels

The state-of-the-art in testing of the very large scale integrated (VLSI) circuits was analyzed. Consideration was given to the directed construction of tests at the system level of presentation of the object or the register transfer level in the VHDL language. The class of functional faults considered at the directed construction of a test corresponds to the bit-stuck faults of the VLSI circuit realizations with the elements of the corresponding design libraries. Proposed was a method of directed test design enabling one at the earlier stages of design to analyze testability vs. the technological design libraries used.     

Graph-based evolutionary design of arithmetic circuits

We present an efficient graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as the bit strings used in genetic algorithm (GA) proposed by Holland (1992) and trees used in genetic programming (GP) proposed by Koza et al. (1997). In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. The proposed EGG system can help to simplify and speed up the process of designing arithmetic circuits and can produce better solutions to the given problem     

Efficient temporal processing with biologically realistic dynamic synapses

Synapses play a central role in neural computation: the strengths of synaptic connections determine the function of a neural circuit. In conventional models of computation, synaptic strength is assumed to be a static quantity that changes only on the slow timescale of learning. In biological systems, however, synaptic strength undergoes dynamic modulation on rapid timescales through mechanisms such as short term facilitation and depression. Here we describe a general model of computation that exploits dynamic synapses, and use a backpropagation-like algorithm to adjust the synaptic parameters. We show that such gradient descent suffices to approximate a given quadratic filter by a rather small neural system with dynamic synapses. We also compare our network model to artificial neural networks designed for time series processing. Our numerical results are complemented by theoretical analyses which show that even with just a single hidden layer such networks can approximate a surprisingly large class of nonlinear filters: all filters that can be characterized by Volterra series. This result is robust with regard to various changes in the model for synaptic dynamics.