一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise

Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) phase noise spectrum. We investigate the origins of these phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and$bf 1/f$noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The phase noise spectrum needed for computing jitter may be obtained from analytical phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements.     

Analysis of the PLL jitter due to power/ground and substrate noise

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.     

Optimization of symbol timing recovery for QAM data demodulators

This paper describes an effective technique for the optimization of the clock recovery circuit in an all-digital modem for linearly modulated signals. Starting from the concept of prefiltering of the data signal (already pursued by these authors in the context of analog data receivers), it is shown how to design an optimum digital prefilter for the minimization of jitter due to both Gaussian and pattern noise in the closed-loop clock recovery scheme by Gardner (1986). The numerical results of the theoretical analysis, obtained after iterative resolution of a constrained-minimum problem via the Lagrange multiplier method, are checked by simulation and can be nicely justified by the consideration of the frequency response of the optimum prefilter. The key outcome of such an approach is the demonstration of a substantial performance improvement in terms of steady-state clock jitter, even with remarkably simple FIR prefilters with a small number of taps     

Phase Noise and Jitter in CMOS Ring Oscillators

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker ($1/f$) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.     

基于频谱平均法的ADC模块性能评估

采用频谱平均法分析时钟抖动和加性白噪声对ADC(A/D转换器)模块噪声基底的影响,推导出噪声基底的数学公式,并通过仿真验证了其正确性。结合公式,改变信号频率或采样频率进行采样,绘出相应的噪声基底频谱,观测噪声基底的变化,可以推断出时钟抖动和加性白噪声的影响,借此评价采样保持电路和外围电路的性能,决定是否要对其进行改进。仿真分析表明,这是一种评估ADC系统性能的好方法,为其改进提供了理论支持。     

A performance analysis of an all-optical clock extraction circuitbased on Fabry-Perot filter

A performance analysis of an optical clock extraction circuit based on a Fabry-Perot filter (FPF) is presented. Two analytical methods, time-domain and frequency-domain analysis, are developed in this paper. Time-domain analysis shows that there is no phase jitter in the extracted optical clock if the free spectral range (FSR) of the FPF is exactly equal to the signal clock frequency. Based on this, we obtain an analytical expression for root mean square (rms) amplitude jitter of the extracted optical clock in time domain, in which we have taken the impacts of carrier frequency drift and carrier phase noise into account. When the FSR of the FPF deviates from the signal clock frequency, both phase jitter and amplitude jitter will occur in the extracted optical clock. In this situation, a more general frequency-domain method is developed to deal with the timing performance under the assumption that carrier phase noise is negligible. This method allows us to calculate both rms phase jitter and rms amplitude jitter of the extracted optical clock. Using the developed two methods, we present a detailed numerical investigation on the impacts of finesse of the FPF, carrier frequency drift, resonator detuning, carrier phase noise, and optical pulse chirp on the timing performance. Finally, the application of this circuit in multiwavelength clock recovery is discussed     

变容二极管背靠背拓扑结构的性能分析

针对变容二极管在实际应用电路中,由于非线性所造成的寄生调制、频率抖动、频率失真、AM to PM噪声引入等问题,文中采用变容二极管背靠背拓扑结构(BBS),通过改善压控线性度来降低电路RF调制、频率抖动、相位噪声等影响,既能抑制非线性导致的寄生调制现象,又简化了调节电压。为目前广泛应用变容管作为电调元件的电路提供了参考。     

An analytical formulation of phase noise of signals with Gaussian-distributed jitter

The output of many oscillatory systems can be approximated by a stochastic square-wave signal with noise-free amplitude and Gaussian-distributed jitter. We present an analytical treatment of the phase noise of this signal with white and Lorentzian jitter spectra. With a white jitter spectrum, the phase noise is nearly Lorentzian around each harmonic. With a Lorentzian jitter spectrum, it is a sum of several Lorentzian spectra, a summation that has a 1/f/sup 4/ shape at far-out frequencies. With a combination of the two, it has 1/f/sup 4/ and 1/f/sup 2/ shapes at close-in and far-out frequencies, respectively. In all cases, the phase noise at the center frequency and the total signal power are both finite. These findings will improve our understanding of phase noise and will facilitate the calculation of phase noise using time- domain jitter analysis.     

Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling /spl Delta//spl Sigma/ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the /spl Delta//spl Sigma/ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the /spl Delta//spl Sigma/ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order /spl Delta//spl Sigma/ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-/spl mu/m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.     

Phase-noise-free coherent optical communication system utilizingdifferential polarization shift keying (DPolSK)

An optical communication system utilizing differential polarization modulation, which is free from phase noise, is discussed. The system proved to be immune to essentially all phase jitter. Separate square operations for the x and y channels, followed by multiplication of the two-channel outputs, effectively removed phase jitter. The delay-and-multiply circuit was directly incorporated in the paths of the frequency shifter and the coupler to the local oscillator laser, minimizing the optical power loss     

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI

This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.     

Analysis of a serial symbol timing recovery technique employingExclusive-OR circuit

An analysis is presented of the performance of a serial symbol timing recovery (STR) circuit which employs an Exclusive-OR circuit for conventional coherent digital modulated communication systems. The output of the timing circuit is a nearly sinusoidal wave whose zero crossings indicate the appropriate sampling instants for extraction of the data. Assuming that the data pulses entering the timing path are even symmetric, exact analytical expressions for the mean and mean-squared values of the timing wave and for the RMS phase jitter are derived as a function of various system parameters such as channel band limiting, postfiltering, delay element, and power spectral density of noise. Numerical results, also checked by computer simulations, show that considerable improvement can be obtained in jitter performance, in addition to the advantages over other STR techniques of lower cost and simpler hardware implementation     

A high-speed, low-power clock generator for a microprocessorapplication

This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 μm process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than ±100 ps     

一种高精度低温漂振荡器设计

针对无线通信和微机械传感器系统对时钟相位噪声的要求,设计了一种高精度低温漂的振荡器电路设计。利用Leeson线形相位噪声模型分析相位噪声,降低了主要噪声源,达到优化相位噪声的目的。该电路在华润上华018 μm工艺平台上流片验证。测试结果显示,电源电压在22~36 V变化,温度在-35~85 ℃变化,频率变化为-2％～+05％;相位噪声-116 dBc＠1 kHz;4 000个周期的抖动在-12%～+12%。该电路已成功集成到微机械陀螺仪控制芯片中。     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

A low noise 0.9 GHz FBAR clock

A low noise 0.9 GHz FBAR clock consisting of an oscillator and divider circuit for single-sided-to-differential conversion for a high-speed interleaved pipeline A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 μm CMOS process, and tested. The circuit showed very good jitter and phase noise performance. A temperature coefficient of –47 ppm/K was measured.     

A 4-GHz clock system for a high-performance system-on-a-chip design

A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PLL) output clock. Jitter can be minimized by regulating the supply to the PLL's noise-sensitive analog circuit blocks in order to filter out supply noise. This paper introduces a PLL-based clock generator intended for use in a high-speed highly integrated system-on-a-chip design. The generator produces clocks with accurate duty cycles and phase relationships by means of a high-speed divider design. The PLL also achieves a power-supply rejection ratio (PSRR) greater than 40 dB while operating at frequencies exceeding 4 GHz. The high level of noise rejection exceeds that of earlier designs by using a combination of both passive and active filtering of the PLL's analog supply voltage. The PLL system has been integrated in a 0.15-μm single-poly 5-metal digital CMOS technology. The measured performance indicates that at a 4-GHz output frequency the circuit achieves a PSRR greater than 40 dB. The peak cycle-to-cycle jitter is 25 ps at 700 MHz and a 2.8-GHz VCO frequency with a 500-mV step on the regulator's 3.3-V supply. The total power dissipated by the prototype is 130 mW and its active area is 1.48×1.00 mm²     

Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.     

基于AD9208的高速采集电路设计

针对大带宽采样需求,设计了基于AD9208的高速采集电路,通过分析时钟抖动,噪声等因素对采集电路的影响,设计了相关电路,包括低抖动时钟电路、模拟信号输入电路、电源电路,并测试了在不同输入频率下,AD9208的无杂散动态范围.