基于FPGA的雷达信号实时预分选方法

本文提出了一种基于关联比较器的雷达信号分选方法,详细阐述了在VirtexII系列FPGA内实现基于内容可寻址存储器(CAM)的关联比较器的途径,并介绍了系统接口设计及调试方法。     

基于FPGA的雷达信号实时预分选方法

本文提出了一种基于关联比较器的雷达信号分选方法，详细阐述了在VirtexⅡ系列FPGA内实现基于内容可寻址存储器(CAM)的关联比较器的途径，并介绍了系统接口设计及调试方法。     

高分辨率雷达显示坐标变换及相关设计

雷达信号处理的实时性要求高效,高速的地址变换方案,概述了一种用于高分辨率雷达显示坐标的快速变换方法,以及硬件实现的相关设计。     

基于CAM的实时脉冲去交错方法研究

本文在简要介绍雷达截获系统传统脉冲去交错方法的基础上,阐述了基于内容可寻址存储器（CAM）的基本原理及其在实时脉冲去交错领域的应用,以Virtex系列FPGA为例提出了三种在可编程路上实现CAM的方法。     

雷达截获系统基于内容可寻址存储器的实时脉冲去交错方法研究

在在简要介绍雷达截获系统传统脉冲去交错方法的基础上,阐述了基于内容可寻址存储器（CAM）的基本原理及其在实时脉冲去交错领域的应用,以Virtex系列FPGA为例提出了三种在可编程器件上实现CAM的方法。     

基于RocketMQ的认知雷达对抗数据交换系统设计

相比于传统雷达对抗系统,认知雷达对抗系统更加灵活多态,功能模块更加复杂,且能快速适应雷达状态的变化,从而对数据交换的要求显著提升。RocketMQ作为一种基于队列模型的消息中间件,具有高可靠、安全性、低延时、可重构等优点。在认知雷达对抗系统实现框架的基础上,设计并实现了一种基于RocketMQ的认知雷达对抗数据交换系统,最后对数据交换系统的性能和可靠性进行了测试,验证了该系统的优越性。     

基于System Generator的雷达干扰信号模拟

针对雷达干扰信号模拟中算法设计快速验证的应用需求,为降低系统可重构开发中的复杂程度,研究了一种基于System Generator模型的FPGA设计开发方法,并以噪声调频和噪声卷积算法实现。对应用实例进行了设计演示验证,为雷达干扰信号算法验证实验提供技术参考。     

一种二维有源相控阵雷达信号处理机的设计

为了满足二维有源相控阵雷达信号处理机快速和实时性的需求,本文设计和实现了一种基于DSP和FPGA的二维有源相扫雷达信号处理机.本信号处理机采用多核DSP搭配FPGA的设计架构,实现了高性能实时信号处理平台,可满足雷达系统算法需求,具有较高的实用性.     

雷达模拟器控制软件的设计与实现

给出了一种雷达模拟器控制软件的设计和实现方法。针对几个关键性问题设计了几种可行的方案 ,并定性分析了其中主要的影响因素 ,比较了优劣 ,最后确定较优的实现方法。该雷达模拟器控制软件设计方案能够快速模拟大批量目标的回波特性 ,回波内可以包含丰富的信息 ,模拟精度较高 ,平均性能较好 ,从而为进一步提高雷达模拟器性能提供软件上的支持。该设计方案已经在项目中采用 ,并正常运行 ,客观地证明了它的可行性和有效性     

一种用于多目标定位的MIMO雷达快速功率分配算法

为了满足实际需求,该文提出一种用于多目标定位的功率分配算法,实现MIMO雷达有限功率的快速优化分配。该文首先给出了多目标定位误差的克拉美罗下界,并将其作为代价函数进行功率分配。而后,设计了一种可应用于多目标定位功率分配的交替全局优化算法,通过搜索Pareto解集来实现功率的快速分配。最后,仿真结果表明,所提的算法能快速实现MIMO雷达有限功率的优化分配,明显提升多目标定位精度。     

Low-power content addressable memory design using two-layer P-N match-line control and sensing

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs.     

CAM辅助的哈希表查找性能分析

现有大规模IP流处理方式中,哈希机制极具优势而在高速网络环境下被广泛采用,但其查找性能直接受限于访存次数。该文主要研究了CAM(Content Addressable Memory)辅助的哈希表(CAHT)查找性能。利用合理的近似,推导了单函数CAHT查找时平均访存次数的理论下限;结合单函数CAHT的分析结论给出了多函数CAHT查找时达到平均访存次数最小的条件。最后,使用实际网络数据验证了分析结果的有效性,为准确评估CAHT处理能力提供了必要的理论依据。     

基于环形结构的联想记忆网络

本文针对ＢＡＭ和ＴＡＭ网络处理数据串联想时的困难和不足，提出了一种基于环形结构的联想记忆网络，称为环形联想记忆网络（ＣＡＭ），给出了网络的拓扑结构和网络的三种基本联想模式，讨论了存储网络连接权所需要的存储量，并与ＢＡＭ和ＴＡＭ联想记忆网络进行了比较，最后给出了实验研究的结果。     

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

With a great scalability potential, nonvolatile magnetoresistive memory with spin-torque transfer (STT) programming has become a topic of great current interest. This paper addresses cell structure design for STT magnetoresistive RAM, content addressable memory (CAM) and ternary CAM (TCAM). We propose a new RAM cell structure design that can realize high speed and reliable sensing operations in the presence of relatively poor magnetoresistive ratio, while maintaining low sensing current through magnetic tunneling junctions (MTJs). We further apply the same basic design principle to develop new cell structures for nonvolatile CAM, and TCAM. The effectiveness of the proposed RAM, CAM and TCAM cell structures has been demonstrated by circuit simulation at 0.18 $ mu$m CMOS technology.      

TCAM/CAM-QCA: (Ternary) Content Addressable Memory using Quantum-dot Cellular Automata

This paper describes a Content Addressable Memory (CAM) architecture and its ternary variant called Ternary Content Addressable Memory (TCAM) using the Quantum-dot Cellular Automata (QCA). QCA is an alternative to the current integrated circuit (CMOS) paradigm based on the characteristics of confinement and mutual repulsion between electrons. It is expected to run with clocks in high frequency (in THz order), in nanometers scale and with very low energy consumption. First, this work presents the basic building blocks (1-bit memory cell, array of memory cells, ternary memory line and encoder). Then, we describe the complete TCAM and CAM architectures. Finally, the proposed architectures are tested and validated using QCADesigner simulator, attesting their functionalities. If QCA consolidates as a possible CMOS substitute, this study can impact the design of future components that uses TCAM and CAM such as routers and switches respectively.     

基于FPGA的在线可写CAM存储器设计

简述了CAM存储器(Content Addressable Memory)的主要应用,讨论了采用可编程器件FPGA设计CAM的一般方法和优缺点,针对FPGA设计的CAM不易在线写入的问题,提出了利用FPGA中查找表LUT设计存储单元,实现CAM内容在线可写的新方法。详细论述了基于Xilinx公司最新FPGA设计实现在线可写CAM的技术,通过设计实例验证了方法的实用性,分析了资源消耗和访问速度,表明该方法设计的CAM资源利用率较高、访问速度快、设计方法容易、易于扩展,能够满足内容在线可写的应用要求。     

Hybrid-Type CAM Design for Both Power and Performance Efficiency

Content-addressable memory (CAM) is a hardware table that can compare the search data with all the stored data in parallel. Due to the parallel comparison feature where a large amount of transistors are active on each lookup, however, the power consumption of CAM is usually considerable. This paper presents a hybrid-type CAM design which aims to combine the performance advantage of the NOR-type CAM with the power efficiency of the NAND-type CAM. In our design, a CAM word is divided into two segments, and then all the CAM cells are decoupled from the match line. By minimizing both the match line capacitances and switching activities, our design can largely reduce the power consumption of CAM. The experimental results show that the hybrid-type CAM can reduce the search energy consumption by roughly 89% compared to the traditional NOR-type CAM. Because the hybrid-type CAM provides a fast pull-down path to speed up the lightweight match line discharge, the search performance of our design is even better than that of the traditional NOR-type CAM.     

A novel constellation amplitude modification method for PAPR reduction in OFDM systems

In this paper, we propose a constellation amplitude modification (CAM) method to reduce the peak‐to‐average power ratio (PAPR) in orthogonal frequency division multiplexing systems. The key idea of the proposed CAM method is to modify the original constellation amplitude and choose the constellation points with the minimum PAPR as the transmitted constellation points. The CAM method formulates the PAPR reduction as a convex optimization problem, and then, it applies the customized interior‐point method to solve the optimization problem. Compared with the traditional methods, the CAM method does not increase the transmit power, and the receiver has no additional operations. Simulation results show that the CAM method converges fast and offers significant PAPR reduction. Copyright © 2016 John Wiley & Sons, Ltd.